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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
| dc.contributor.author | Tahsin Türker Mutlugün | en |
| dc.contributor.author | 穆達新 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:22:57Z | - |
| dc.date.available | 2016-03-09 | |
| dc.date.copyright | 2014-03-09 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-01-24 | |
| dc.identifier.citation | [1] I. Abdou and W. Pratt. Quantitative design and evaluation of enhancement/thresh- olding edge detectors. Proceedings of the IEEE, 67(5):753–763, 1979.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58629 | - |
| dc.description.abstract | 針對 FPGA 所做的高階合成方法已被廣泛地運用於高效能運算上。 隨著 OpenCL 的推出，一些高階合成的研究已經轉向將 OpenCL 引入 FPGA 來使用。本論文提出一個適用於 FPGA 的 OpenCL 架構並且著 重於記憶體存取的改善以達成最佳效能的目標。在 OpenCL 的計算區 塊裡，執行時間與區域記憶體的存取延遲時間總是存在著一個線性關 係，而這延遲時間一般會以增加平行工作量來彌補的，然而這樣的方 法很容易地就會耗盡 FPGA 上的資源。因此本文使用無衝突的多埠記 憶體，藉此將區域記憶體的存取延遲時間減至最少。實驗結果顯示多 埠記憶體能成功地提高運算速度並減少所需的平行工作量到一個可行 值來提供最高產量。 | zh_TW |
| dc.description.abstract | High-Level Synthesis (HLS) targeting FPGAs has been widely used for high performance computing. With the introduction of OpenCL, some of the HLS research have shifted towards bringing OpenCL to FPGAs. This thesis presents an OpenCL architecture for FPGAs and focuses on memory access improvements with the goal of achieving optimal performance. In OpenCL compute blocks, there is usually a linear relation between computation time and local memory access latency. This latency is normally hidden by increas- ing the parallel workload. However, with such an approach, target FPGA device could easily run out of resources. In this work, conflict-free multi- ported memories have been used instead to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for max- imum throughput to practical amounts. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:22:57Z (GMT). No. of bitstreams: 1 ntu-103-R00921087-1.pdf: 3528233 bytes, checksum: a75bebebd10fdbe799053e53e29d4b85 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii Acknowledgements iii 摘要 iv Abstract v 1 Introduction 1 1.1 Motivation 2 1.2 Related Work 4 1.3 Contributions 5 2 Background 7 2.1 OpenCL Architecture 7 2.1.1 Platform Model 7 2.1.2 Execution Model 8 2.1.3 Memory Model 9 2.2 Hardware Acceleration 10 2.2.1 Memory Optimization 11 3 OpenCL on FPGA 15 3.1 Host-Device Interface 15 3.2 Execution 16 3.2.1 Compute Unit 17 3.2.2 Processing Element 18 3.3 Memory Hierarchy 19 3.3.1 Global Memory 19 3.3.2 Local Memory 22 3.3.3 Private Memory 23 3.4 Multiported Memories 23 3.4.1 Multipumping 24 3.4.2 Live-Value Table 24 4 Experimental Results 29 4.1 Experimental Setup 29 4.2 Multiported Memory Results 30 4.3 Performance 32 4.3.1 Matrix Multiplication 33 4.3.2 Sobel Edge Detector 39 4.3.3 Discrete Cosine Transform 43 5 Conclusion 49 5.1 Summary 49 5.2 Future Work 50 Bibliography 51 | |
| dc.language.iso | en | |
| dc.title | OpenCL在可程式邏輯陣列上運算使用多埠共享記憶體 | zh_TW |
| dc.title | OpenCL Computing on FPGA Using Multiported Shared Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆(Chin-Laung Lei),顏嗣鈞(Hsu-Chun Yen),洪士灝(Shih-Hao Hung),郭斯彥(Sy-Yen Kuo) | |
| dc.subject.keyword | OpenCL,課程式陣列邏輯,多埠記憶體,高級綜合, | zh_TW |
| dc.subject.keyword | OpenCL,FPGA,Multiported Memory,High-Level Synthesis, | en |
| dc.relation.page | 54 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-01-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-103-1.pdf 目前未授權公開取用 | 3.45 MB | Adobe PDF |
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