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標題: | 以現場可程式邏輯陣列實現路徑時序偏差之校正 Implementation of an FPGA-Based Deskew Technique |
作者: | Chung-Hung Lin 林俊宏 |
指導教授: | 黃俊郎 |
關鍵字: | 半導體自動測試機台,路徑時間偏差,現場可程式邏輯陣列,延遲線, ATE,TIiming Skew,FPGA,Delay Line, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 隨著製程與封裝技術的進步,使得晶片接腳數量增多,直接影響到半導體自動測試機台 (ATE) 的測試通道數必需增加,測試功能電路板和待測晶片載板的佈線密度勢必提高,使得印刷電路板設計難度提高,成本也跟著大幅提升,且印刷電路板上電路和機構特性上的影響,使得電路會有路徑時間偏差 (Skew) 的問題存在,會造成測試時序錯誤,測試成本提高。
綜合以上問題,需有方法來實現路徑時間偏差的校正功能,讓測試時序的精準度提高,且此方法可使待測晶片載板設計規範放寬,設計難度降低,並降低成本。但目前的校正技術都屬於較高成本或開發時程較長且使用上較不具彈性變動使用,如開發ASIC、專用校正載板或使用外部時序量測儀器。 所以本論文提出以DE2-70 Altera Cyclone II FPGA來實現路徑時序偏差的校正功能,以符合成本較低且使用彈性較高的原則,其主要架構由個人電腦與FPGA共同完成量測的工作,FPGA硬體則由Wishbone匯流排、延遲線 (Delay Line) 電路和控制電路等組成,其中延遲線電路為主要的部份,其解析度會影響到所量測出路徑延遲的準確度,所以選擇LUT-Based的延遲線,其解析度可達15ps,因量測出的數值呈常態機率累積分佈函數,可直接推估得出路徑時序偏差值,再結合圖形化使用者介面的控制和計算,可將校正程序自動化,並在得到補償值後自動補償,驗證後得到的路徑時序偏差可縮小至55ps。 With the advance of processing and packaging technology, integrated chip pin counts rise to meet higher demands. To cope with the trend in IC production, the number of test channels on automatic test equipment has to grow. Such changes would directly impact the routing density on both the function board and DUT load board, causing it to become a challenge in board level design and cost management. As a result, the test equipment often suffers path skews due to loading and mechanical effects, resulting in timing error in test sequences. To reduce the load board design complexity and cost, we need a way to calibrate path skew to improve timing accuracy so that we can relax the PCB design constraints. However, the deskew technique in ATE , such as ASIC, dedicated calibration load board or by external equipment, is very expensive and incurs long development time. The FPGA-based de-skew technique is a promising one due to its low cost and flexibility. The publication proposes a path deskew technique implemented with DE2-70 Altera Cyclone II FPGA and a PC in order to meet the low cost and flexibility. The FPGA system consists of Wishbone bus, Delay Line and counter. The delay line determines the outcome of the experiments, for which its resolution has a directly impact on the accuracy of the measurement. We selected the LUT-Based Delay with 15ps for the deskew system. Because of the measured values were normal cumulative distribution function, path delays can be obtained deriving the cumulative distribution function mean. Experiment processes, including circuit control and data calculation, were done and automated on a self-written program with graphic user interface (GUI). After compensating the skew, we can get the accuracy less than 55ps. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58509 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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