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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
| dc.contributor.author | Wei-Che Tsai | en |
| dc.contributor.author | 蔡偉哲 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:16:29Z | - |
| dc.date.available | 2019-02-26 | |
| dc.date.copyright | 2014-02-26 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-02-11 | |
| dc.identifier.citation | [1]C. Altera, 'Nios II C2H Compiler User Guide,' 2009.
[2] C. Altera, 'Altera SDK for OpenCL Getting Started Guide,' 2013. [3] H. Chu-Yi, C. Yen-Shen, L. Youn-Long, and H. Yu-Chin, 'Data path allocation based on bipartite weighted matching,' in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 499-504. [4] J. Cong and Z. Zhiru, 'An efficient and versatile scheduling algorithm based on SDC formulation,' in Design Automation Conference, 2006 43rd ACM/IEEE, 2006, pp. 433-438. [5] K. Group, 'the open standard for parallel programming of heterogeneous systems (OpenCL).' [6] H. Qijing, L. Ruolong, A. Canis, C. Jongsok, R. Xi, S. Brown, et al., 'The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs,' in Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on, 2013, pp. 89-96. [7] C. Xilinx, 'Vivado High-Level Synthesis User Guide,' 2012. [8] A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. H. Anderson, et al., 'LegUp: high-level synthesis for FPGA-based processor/accelerator systems,' presented at the Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, Monterey, CA, USA, 2011. [9] S. Hadjis, A. Canis, J. H. Anderson, J. Choi, K. Nam, S. Brown, et al., 'Impact of FPGA architecture on resource sharing in high-level synthesis,' presented at the Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, Monterey, California, USA, 2012. [10] A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, T. Czajkowski, et al., 'LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems,' ACM Trans. Embed. Comput. Syst., vol. 13, pp. 1-27, 2013. [11] S. Steinke, L. Wehmeyer, L. Bo-Sik, and P. Marwedel, 'Assigning program and data objects to scratchpad for energy reduction,' in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 409-415. [12] R. Banakar, S. Steinke, L. Bo-Sik, M. Balakrishnan, and P. Marwedel, 'Scratchpad memory: a design alternative for cache on-chip memory in embedded systems,' in Hardware/Software Codesign, 2002. CODES 2002. Proceedings of the Tenth International Symposium on, 2002, pp. 73-78. [13] M. Verma, L. Wehmeyer, and P. Marwedel, 'Cache-aware scratchpad allocation algorithm,' in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, pp. 1264-1269 Vol.2. [14] A. Janapsatya, S. Parameswaran, Ignjatovic, x, and A., 'Hardware/software managed scratchpad memory for embedded system,' in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 370-377. [15] V. Suhendra, T. Mitra, A. Roychoudhury, and C. Ting, 'WCET centric data allocation to scratchpad memory,' in Real-Time Systems Symposium, 2005. RTSS 2005. 26th IEEE International, 2005, pp. 10 pp.-232. [16] G. Zhi and W. Najjar, 'A Compiler Intermediate Representation for Reconfigurable Fabrics,' in Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, 2006, pp. 1-4. [17] J. F. Deverge and I. Puaut, 'WCET-Directed Dynamic Scratchpad Memory Allocation of Data,' in Real-Time Systems, 2007. ECRTS '07. 19th Euromicro Conference on, 2007, pp. 179-190. [18] Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, 'CHStone: A benchmark program suite for practical C-based high-level synthesis,' in Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, 2008, pp. 1192-1195. [19] J. Villarreal, A. Park, W. Najjar, and R. Halstead, 'Designing Modular Hardware Accelerators in C with ROCCC 2.0,' in Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on, 2010, pp. 127-134. [20] C. Pilato and F. Ferrandi, 'Bambu: A modular framework for the high level synthesis of memory-intensive applications,' in Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on, 2013, pp. 1-4. [21] P. Coussy, D. D. Gajski, M. Meredith, and A. Takach, 'An Introduction to High-Level Synthesis,' Design & Test of Computers, IEEE, vol. 26, pp. 8-17, 2009. [22] LLVM Compiler Infrastructure. Available: http://llvm.org [23] LP_solve Available: http://lpsolve.sourceforge.net/ [24] (2004). SUIF Compiler System. Available: http://suif.stanford.edu [25] Altera Quartus Synthesis toolchain. Available: http://www.altera.com [26] C. Lattner. The Architecture of Open Source Applications. Available: http://www.aosabook.org/en/llvm.html | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58475 | - |
| dc.description.abstract | 高階合成的編譯器通常可以生成幾種不同的硬體讓使用者選用，然而編譯器預設的硬體架構不可能適應所有使用者的需求。我們提出了一個使用者易於客制化的硬體架構，其中的編譯器是修改自LegUp高階合成編譯器且加上暫存記憶體來加速編譯器所產生的硬體，此外我們使用雙埠記憶體來增強效能。暫存記憶體內容的選擇則是由一個基於線性規劃的演算法來決定，此演算法在編譯時分析源始碼以求得一個最佳化的記憶體配置。實驗的結果展示使用暫存記憶體後，程式執行的時間只需原本只用SDRAM時的23%~43%，而且使用SDRAM加上暫存記憶體可以解決比較大的問題。 | zh_TW |
| dc.description.abstract | High-level synthesis (HLS) compilers usually provide some supported target architectures that can be chosen by users; however, the limited architectures may not fit the requirements of underlying systems. In this paper, we propose a target architecture embedded with a scratchpad memory (SPM) and an SDRAM that allows users to customize their design. The proposed architecture has been integrated with an HLS compiler, called LegUp, so that the synthesizing computation can be executed on the target architecture with the SPM and the SDRAM. In addition, we use a dual port memory controller to enhance the performance of the target architecture. An algorithm based on integer linear programming is used to allocate data to the proposed SPM at compile time. The experiment results show that the proposed architecture can effectively achieve the 23%~43% execution time of an architecture without an SPM, and can solve huge problems by using the external memory. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:16:29Z (GMT). No. of bitstreams: 1 ntu-103-R00921080-1.pdf: 4755967 bytes, checksum: f5dd0db83e330b70edd90abdbc575a39 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
摘要 ii Abstract iii Chapter 1. Introduction 1 1.1 Research object 2 1.2 Thesis organization 3 Chapter 2. Related Work 3 2.1 High level synthesis 4 2.2 Scratchpad memory 6 Chapter 3. Background 8 3.1 LLVM 8 3.2 LegUp 10 3.2.1 Hardware Architecture of LegUp 10 3.2.2 Software Architecture of LegUp 11 3.3 Quartus II compiler tool chain 12 3.3.1 Qsys System Design tool 12 3.3.2 Avalon-MM interface 13 3.4 Linear program 14 Chapter 4. Methodology 15 4.1 Design flow 15 4.2 Target Architecture 17 4.3 SPM allocation algorithm 18 4.4 Scheduler 21 4.5 Integrate the HLS compiler into Qsys 23 Chapter 5. Experiment & Results 25 5.1 Experiment setup 25 5.2 SDRAM and SPM with shared bus 25 5.3 Dual Ports architecture 27 5.4 Scratchpad memory allocation 31 5.5 Area report 35 Chapter 6. Conclusions 37 Reference 38 | |
| dc.language.iso | en | |
| dc.title | 以暫存記憶體整合高階合成編譯器支援的FPGA硬體架構 | zh_TW |
| dc.title | A Scratchpad Memory for High-Level Synthesis Compiler on FPGA | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪士灝,雷欽隆 | |
| dc.subject.keyword | 高階合成,編譯器,暫存記憶體,FPGA, | zh_TW |
| dc.subject.keyword | High-level Synthesis,Compiler,Scratchpad Memory,FPGA, | en |
| dc.relation.page | 40 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-02-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-103-1.pdf 目前未授權公開取用 | 4.64 MB | Adobe PDF |
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