針對內部缺陷的時序感知邏輯閘轉態窮舉測試向量選擇

Abstract

在先進製程中，標準元件內部的缺陷(cell-internal defects)越來越受到重視，常用來模擬缺陷的錯誤模型(fault model)都假設缺陷發生在標準元件與標準元件之間；除此之外現在也需要準確的公式來模擬微小延遲缺陷(samll delay defect)以及內部缺陷，部分的內部缺陷可以使用微小延遲缺陷模型來模擬。此論文提出一個針對內部缺陷的時序感知邏輯閘轉態窮舉測試向量選擇器；我們的 TARGET 測試向量結合了標準元件感知(Cell-aware)以及時序感知(Timing-aware)兩個自動測試向量產生器的優點，他試圖使用不同的邏輯閘輸入端組合引發相同的邏輯閘轉態。我們提出了 TARGET 涵蓋率(Coverage)以及 TARGET 統計延遲程度(SDQL)去衡量產生的測試向量品質。TARGET 並不需要窮舉每個標準元件使用以積體電路為重點的模擬程式(SPICE)，與傳統 N 次偵測以及時序感知自動測試向量比起來，TARGET測試向量有較好的 TARGET 測試涵蓋率以及較短的測試向量數。

In advanced technology, cell-internal defects gain more attention than before. Those well-known fault models all assume defects are between standard library cells. Besides, accurate metric is needed for modeling small delay defects and internal defects. Some cell-internal defects can be modeled as small delay faults. This thesis presents a timing-aware gate exhaustive transition fault (TARGET) fault simulation and test pattern selection for cell-internal defects. Our TARGET test patterns combine both the benefits of cell-aware and timing-aware ATPG. It tries to launch gate output transitions from as many different gate input transitions as possible. We proposed TARGET coverage and TARGET SDQL to evaluate the quality of our test patterns. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional $N$-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.