PCHB-WCHB-PCFB類延遲非敏感混合電路合成

Abstract

隨著半導體科技的演進，積體電路製程越來越進步，時脈和時間變異問題漸漸成為積體電路設計者的挑戰。 迫使積體電路設計者花費更多心力尋找可行的解決方法，而積體電路設計者將非同步電路設計視為一種可作為替代的解決方法。 在非同步電路眾多的延遲模型中，類延遲非敏感(quasi-delay insensitive)模型被視為一種可行的模型，因為它有時間健全的特性，在設計時只需要少數的時間假設。 雖然類延遲非敏感電路受到時間變異的影響不大而且容易對時間執行驗證，然而對面積需求較大這個缺點卻可能抵消類延遲非敏感電路在效能以及功率消耗相對同步電路上的優勢，這個問題成為類延遲非敏感電路推廣使用上的阻礙。 這篇論文中，我們提出一種保守且有效率的靜態效能分析方法以及一種使用預先充電半緩衝器(pre-charged half buffer)以及弱狀態半緩衝器(weak conditioned half buffer)的合成流程。 實驗結果顯示我們的效能分析方法很有效率而且合成流程在時間條件下可以有效的減少面積消耗。

The difficulty of synchronization and the increase of timing variability have being made IC design more and more challenging. Asynchronous design methodologies become a natural solution to these challenges. Among various asynchronous delay models, quasi-delay insensitive (QDI) circuits are promising due to their relaxed timing assumption and timing robustness. Although the QDI design style is strong against timing variability and easy for timing verification, its large area overhead, however, may nullify its advantages on performance improvement and power reduction, and the overhead remains a major obstacle against its adoption. In this thesis, we address the above issue of QDI circuit optimization and propose a synthesis flow for pre-charged half buffer (PCHB), weak conditioned half buffer (WCHB) and pre-charged full buffer (PCFB) circuit synthesis. Experimental results show efficient performance analysis and effective area reduction under cycle time constraints.