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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳瑞北 | |
dc.contributor.author | Chang-Wei Lo | en |
dc.contributor.author | 羅昌瑋 | zh_TW |
dc.date.accessioned | 2021-06-16T05:17:20Z | - |
dc.date.available | 2014-08-25 | |
dc.date.copyright | 2014-08-25 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-17 | |
dc.identifier.citation | [1] S. H. Hall and H. L. Heck, “Advanced signal integrity for high-speed digital designs,” New York, NY, USA: Wiley, 2009, pp. 121–129.
[2] S. H. Hall and H. L. Heck, “Advanced signal integrity for high-speed digital designs,” New York, NY, USA: Wiley, 2009, Chap 13. [3] W.-D. Guo, J.-H. Lin, C.-M. Lin, T.-W. Huang, and R.-B. Wu, “Fast methodology for determining eye diagram characteristics of lossy transmission lines,” IEEE Trans. Adv. Packag., vol. 32, no. 1, pp. 175–183, Feb. 2009 [4] S.-Y. Huang, Y.-S. Cheng, K.-Y. Yang, and R.-B. Wu, “Fast prediction and optimal design for eye-height performance of mismatched transmission lines,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 4, no. 5, pp.896-904, May 2014 [5] K.-Y. Yang, C.-B. Chang, T.-Y. Wu, W.-S. Wang, Y.-H. Lin, and R.-B. Wu, 'Modeling and fast eye diagram estimation of ringing effects on branch line structures,' IEEE Trans. Compon., Packag. Manuf. Technol., vol.4, no.4, pp.641,647, April 2014 [6] A. B. Kahng and V. Srinivas, “Mobile system considerations for SDRAM interface trends,” in Proc. 13th Int. Workshop SLIP, pp. 1–8, Jun. 2011 [7] C.-H. Kim, J. H. Lee, J. B. Lee, B.-S. Kim, C. S. Park, S.-B. Lee, S.Y. Park, C.W. Lee, J.G. Roh, H.S. Nam, D.Y. Kim, D.Y. Lee, T.S. Jung, H. Yoon, S.I. Cho, “A 64-Mbit, 640-MByte/s bidirectional data strobed, double data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1703–1710, Nov. 1998. [8] T. S. Yang, Y. S. Kang, T. L. Song, Y. Ra, S. S. Lee, and W. H. Paik, “Low cost DTV-SoC system implementation using integrated signal integrity analysis,” in Proc. Asia-Pacific Symp. Electromagn. Compat., 19th Int. Zurich Symp. Electromagn. Compat., pp. 259–262, May 2008. [9] A. Deustch, G. V. Kopcsay, P. W. Coteus, C. W. Surovic, P. E. Dahlen, D. L. Heckmann, D.-W. Duan, “Frequency-dependent losses on high performance interconnections,” IEEE Trans. Electromagn. Compat., vol. 43, no. 4, pp. 446–465, Nov. 2001. [10] H. H. Jhuang and T. W. Huang, “Design for electrical performance of wideband multilayer LTCC microstrip-to-stripline transition,” Proc. 6th Electron, Packag. Technol. Conf., Singapore, pp. 506 - 509, Dec. 2004 [11] S. K. K and M. S. Bhat, “Impedance matching for the reduction of via induced signal reflection in on-chip high speed interconnect Lines,” IEEE Int. Commun. Control and Comput. Tech. Conf., Tamilnadu, India, pp. 120-125, Oct. 2010. [12] T. Kushta, K. Narita, T. Kaneko, T. Saeki, and H. Tohya, “Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs,” IEEE Trans. Microw. Wireless Compon. Lett., vol. 13, pp.169-171, May 2003. [13] Z. Shen and J. Tong, “Signal integrity analysis of high-speed single-ended and differential vias,” EPTC 10th Electron. Packag. Technol. Conf., pp.65-70, Dec.2008. [14] W. Humann, “Compensation of transmission line loss for Gbit/s test on ATEs,” Proc. IEEE Int. Test Conf., pp. 430–437, Oct. 2002. [15] G.-H. Shiue, W.-D. Guo, C.-M. Lin, and R.-B. Wu, “Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines,” IEEE Trans. Adv. Packag., vol. 29, no. 3, pp. 560–569, Aug. 2006. [16] K.-T. Hsu, G.-H. Shiue, C.-M. Lin, T.-W. Huang, and R.-B. Wu, “Design of reflectionless vias using neural network-based approach,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 1, pp. 211–218, Feb. 2008. [17] T. K. Wang, S. T. Chen, C.W. Tsai, S. M. Wu, J. J. Drewniak, and T. L. Wu, “Modeling noise coupling between package and PCB power/ground planes with an efficient 2D-FDTD/lumped element method,” IEEE Trans. Adv. Packag., vol. 30, no. 4, pp. 864–871, Nov. 2007. [18] D. G. Kam and J. Kim, “40-Gb/s package design using wire-bonded plastic ball grid array,” IEEE Trans. Adv. Packag., vol. 31, no. 2, pp. 258–266, May 2008. [19] B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes,” in Proc. Symp. IEEE VLSI Circuits, Jun. 2002, pp. 54–57. [20] H.-H. Chuang, W.-D. Guo, Y.-H. Lin, H.-S. Chen, Y.-C. Lu, Y.-S. Cheng, M.-Z. Hong, C.-H. Yu, W.-C. Cheng, Y.-P. Chou, C.-J. Chang, J. Ku, T.-L. Wu, and R.-B. Wu, “Signal/power integrity modeling of high-speed memory modules using chip-package-board coanalysis,” IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp.381-391, May 2010. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56160 | - |
dc.description.abstract | 由於數位信號系統操作頻率不斷地提高的趨勢,使得高速數位信號透過傳輸線傳遞時,因傳遞路徑和佈線方式所引發的各種電氣效應,會造成信號傳輸上的延遲、變形、信號失真等問題。
這些問題造成系統的時序或信號位準產生錯誤進而引發不穩定甚至系統當機的現象,因此信號完整性的評估如今已成為高速數位系統設計非常重要的關鍵。影響信號完整度的雜訊主要有兩種,一種是信號線之間的耦合效應產生的耦合雜訊,另一種則為傳輸線本身或不連續結構造成阻抗不匹配而產生的反射雜訊。因此,本論文提出系統封裝和印刷電路板的設計方案,以求降低雜訊,並提升信號品質。 本論文規格設定在使用兩層電路板及薄型四方扁平式封裝,有別於之前的四層電路板和球柵陣列封裝,主要針對反射雜訊和耦合雜訊進行改良。在一控制器連接二記憶體晶片的電路板上,設計電流源與傳輸線阻抗盡量匹配,和分岔後的傳輸線阻抗稍微高於分岔前的阻抗,皆可有效降低其反射雜訊;而以GSGSG結構的傳輸線取代GSSG結構的傳輸線,不僅大幅降低信號耦合程度,也降低了傳輸線阻抗,使其更容易與電流源阻抗達成匹配。 對於薄型四方扁平式封裝,增加適當數量的接地線,使得鄰近打線之間的耦合效應大幅降低,有效抑制其雜訊,減少封裝連接產生的信號偏差。 本論文同時也探討當以飛躍式佈線連接多個記憶體晶片時,會產生傳輸線阻抗不匹配的問題,造成多重反射而影響信號表現;晶片電容值較小時,提升後面傳輸線特徵阻抗即可改善信號表現;但電容值較大時,需要選擇適當的電源及末端阻抗才能使信號有所改善。 | zh_TW |
dc.description.provenance | Made available in DSpace on 2021-06-16T05:17:20Z (GMT). No. of bitstreams: 1 ntu-103-R01942020-1.pdf: 6020343 bytes, checksum: ee2d86badaaf99a949618ee7a898d833 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 I 中文摘要 II ABSTRACT III CONTENTS V LIST OF FIGURES VIII LIST OF TABLES XIII Chapter 1 緒論 1 1.1 研究動機 1 1.2 文獻探討 2 1.3 章節概述 3 1.4 主要貢獻 4 Chapter 2 印刷電路板架構 5 2.1 模型簡介 5 2.2 優劣分析 7 Chapter 3 新兩層板設計與架構-一控制器對二記憶體 8 3.1 一控制器對兩記憶體之模型簡介 8 3.2 資料線分析與設計 11 3.2.1 資料線介紹 11 3.2.2 資料線串音分析與模型建立 17 3.2.3 地線回流導孔設計 20 3.3 位置線設計與分析 25 3.3.1 位置線簡介 25 3.3.2 串阻設計準則 35 3.4 位置線上振鈴雜訊之模型建立與眼圖估計 40 3.4.1 RLC等效模型的建立 42 3.4.2 眼圖預測與最差情形估計 46 3.5 阻抗不匹配之位置線振鈴雜訊分析 51 3.6 電源阻抗匹配之設計 56 3.7 差模傳輸信號線的訊號完整度分析 59 3.7.1 資料參照線(DQS)訊號完整度分析 59 3.7.2 時脈線訊號完整度分析 63 3.8 總結整理 65 Chapter 4 封裝效應分析與設計 67 4.1 封裝簡介 67 4.2 LQFP打線分析 67 4.3 BGA封裝簡介 74 4.4 BGA和LQFP封裝對信號線傳輸信號之影響 76 4.5 LQFP打線新設計方案 79 4.6 LQFP打線連接新設計信號線的影響 83 4.7 電流源阻抗對眼圖之影響 86 4.8 封裝總結 89 Chapter 5 新兩層板設計與架構-一控制器對八記憶體 90 5.1 一控制器對八記憶體之模型簡介 90 5.2 記憶體晶片電容值較低時之分析 91 5.3 記憶體晶片電容值較高時之分析 97 5.4 記憶體晶片電容值較高時之改善方案 101 5.5 分析總結 109 Chapter 6 結論 110 參考文獻 112 碩士論文口試問題與回答 114 | |
dc.language.iso | zh-TW | |
dc.title | 兩層印刷電路板上第三代雙倍資料率記憶體系統之信號完整度分析與設計 | zh_TW |
dc.title | Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳宗霖,王文山,林丁丙,郭維德 | |
dc.subject.keyword | 信號完整度,封裝,電路板,信號線, | zh_TW |
dc.subject.keyword | signal integrity,PKG,PCB,signal trace, | en |
dc.relation.page | 116 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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