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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55854
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor林宗賢(Tsung-Hsien Lin)
dc.contributor.authorFu-Chien Huangen
dc.contributor.author黃富謙zh_TW
dc.date.accessioned2021-06-16T05:09:33Z-
dc.date.available2017-08-22
dc.date.copyright2014-08-22
dc.date.issued2014
dc.date.submitted2014-08-18
dc.identifier.citation[1]T. Roh, S. Hong, H. Cho, and H. J. Yoo, “A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental health monitoring,” in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 294-296.
[2]F. Zhang, Y. Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, A. Klinefelter, J. Pandey, J. Boley, E. Carlson, A. Shrivastava, B. Otis, and B. Calhoun, “A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC,” in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 298-300.
[3]Y.-J. Huang, T.-W. Lin, T.-H. Tzeng, C.-W. Huang, P.-W. Yen, C.-T. Lin, and S.-S. Lu, “A self-powered CMOS reconfigurable multi-sensor SoC for biomedical applications,” in Symp. VLSI Circuits Dig. Tech. Papers, 2013, pp. 248 -249.
[4]FCC Rules and Regulations, “MedRadio band plan,” Nov. 2011.
[5]S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P. K. Hanumolu, “A 71dB SFDR open loop VCO-based ADC using 2-Level PWM modulation,” in Symp. VLSI Circuits Dig. Tech. Papers, 2011, pp. 270-271.
[6]J. Daniels, W. Dehaene, M. Steyaert, and A. Wiesbauer, “A 0.02mm2 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR,” in Symp. VLSI Circuits Dig. Tech. Papers, 2010, pp. 155-156.
[7]M. Hovin, A. Olsen, T. S. Lande, and C. Toumazou, “Delta-sigma modulators using frequency-modulated intermediate values,” IEEE J. Solid-State Circuits, vol. 32, no. 1, pp.13-22, Jan. 1997.
[8]X. Xing, P. Gao, and G. Gielen, “A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), 2013, pp. 327-330.
[9]A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with time-domain comparator,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 246-247.
[10]S.-K. Lee, S.-J. Park, H.-J. Park, and J.-Y. Sim, “A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 651-659, Mar. 2011.
[11]F. Michel and M. Steyaert, “A 250mV 7.5μW 61dB SNDR CMOS SC ΔƩ modulator using a near-threshold-voltage-biased CMOS inverter technique,” in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 476-477.
[12]L. Dorrer, F. Kuttner, A. Santner, C. Kropf, T. Puaschitz, T. Hartig, and M. Punzenberger, “A continuous time ΔƩ ADC voice coding with 92dB DR in 45nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 502-203.
[13]J. Xu, X. Wu, H. Wang, J. Shen, and B. Liu, “Power optimization of high performance ΔΣ modulators for portable measurement applications,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2010, pp. 1-4.
[14]F. Cannillo, E. Prefasi, L. Hernandez, E. Pun, F. Yazicioglu, and C. V. Hoof, “1.4V 13μW 83dB DR CT-ΣΔ modulator with dual-slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), 2011, pp. 267-270.
[15]A. Iwata and N. Sakimura, “The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 7, pp. 941-945, Jul. 1999.
[16]E. Alon, V. Stojanovic, and M. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 820-828, Apr. 2005.
[17]J. Kim and S.-H. Cho, “A time-based analog-to-digital converter using a multi-phase VCO,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2006, pp. 3934-3937.
[18]M. Z. Straayer and M. H. Perrott, “A 12-bit 10-MHz bandwidth, continuous-time sigma-delta ADC with a 5-Bit, 950-MS/S VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2008.
[19]U. Wismar, D. Wisland, and P. Andreani, “A 0.2V 0.44μW 20kHz analog to digital ƩΔ modulator with 57fJ/conversion FoM,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), 2006, pp. 187-190.
[20]U. Wismar, D. Wisland, and P. Andreani, “A 0.2V, 7.5μW, 20kHz ƩΔ modulator with 69dB SNR in 90nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), 2007, pp. 206-209.
[21]M. Park and M. H. Perrott, “A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time ΔƩ ADC with VCO-based integrator and quantizer implemented in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009.
[22]G. Taylor and I. Galton, “A mostly-digital variable-rate continuous-time delta-sigma modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2634-2646, Dec. 2010.
[23]K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P. K. Hanumolu, “A 16-mW 78-dB SNDR 10-MHz BW CT ΔƩ ADC using residue-cancelling VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2916-2927, Dec. 2012.
[24]S. Rao, K. Reddy, B. Young, and P. K. Hanumolu, “A deterministic digital background calibration technique for VCO-based ADCs,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 950-960, Apr. 2014.
[25]T.-H. Lin and Y.-J. Lai, “An agile VCO frequency calibration technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 340-349, Feb. 2007.
[26]Y.-D. Chang, C.-H. Weng, T.-H. Lin, and C.-K. Wang, “A 379nW 58.5dB SNDR VCO-based ΔΣ modulator for bio-potential monitoring,” in Symp. VLSI Circuits Dig. Tech. Papers, 2013, pp. 66-67.
[27]B. E. Boser and B. A. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.
[28]G. Taylor and I. Galton, “A reconfigurable mostly-digital delta-sigma ADC with a worst-case FOM of 160 dB,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 983-995, Apr. 2013.
[29]W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS self-calibrating frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
[30]M. Z. Straayer and M. H. Perrott, “A multi-path gated ring oscillator TDC with first-order noise shaping,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, Apr. 2009.
[31]J. Kim, T.-K. Jang, Y.-G. Yoon, and S.-H. Cho, “Analysis and design of voltage-controlled oscillator-based analog-to-digital converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp.18-30, Jan. 2010.
[32]S. J. Huang, Y. C. Yeh, H. Wang, P. N. Chen, and J. Lee, “W-Band BPSK and QPSK transceivers with Costas-loop carrier recovery in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3033-3046, Dec. 2011.
[33]W. Z. Chen, T. Y. Lu, W. W. Ou, S. T. Chou, and S. Y. Yang, “A 2.4 GHz reference-less receiver for 1 Mbps QPSK demodulation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 3, pp. 505-514, Mar. 2012.
[34]Y. H. Liu, A. Ba, J.H.C. van den Heuvel, K. Philips, G. Dolmans, and H. de Groot, “A 1.2nJ/b 2.4GHz RX with a sliding-IF phase-to-digital converter for wireless personal/body-area-networks,” in IEEE ISSCC Dig. Tech. Papers, 2014, pp.166-167.
[35]J. Bae, L. Yan, and H.-J. Yoo, “A low energy injection-locked FSK transceiver with frequency-to-amplitude conversion for body sensor applications,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 928-937, Apr. 2011.
[36]Q. Zhu and Y. Xu, “A 228 μW 750 MHz BPSK demodulator based on injection locking,” IEEE J. Solid-State Circuits, vol.46, no.2, pp.416-423, Feb. 2011.
[37]H. Yan, J. G. Macias-Montero, A. Akhnoukh, L. C. N. de Vreede, J. R. Long, and J. N. Burghartz, “An ultra-low-power BPSK receiver and demodulator based on injection-locked oscillators,” IEEE Trans. Microwave Theory Tech., vol. 59, no.5, pp. 1339-1349, May 2011.
[38]Y. L. Tsai, J. Y. Chen, B. C. Wang, T. Y. Yeh, and T. H. Lin, “A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique,” in Symp. VLSI Circuits Dig. Tech. Papers, 2014, pp. 57-58.
[39]B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal of Solid State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55854-
dc.description.abstract在遠距健康照護系統中,可攜式監測裝置必須能以低功率消耗完成擷取生醫信號與無線資料傳輸以期達到長時照顧的目的。
第一部分即提出一個用於生醫信號擷取的小面積、極低功耗之基於壓控振盪器的三角積分調變器。壓控振盪器的非線性轉換通常會造成輸出的諧波失真並降低了無雜散動態範圍和信號對雜訊與失真比。此調變器使用單位元回授迴路與降低輸入振幅之方式來降低壓控振盪器的非理想效應。而為使調變器能有最大操作區域且避免信號轉換失真,壓控振盪器中心頻率需為取樣頻率的整數倍。因此,此處提出一個快速頻率校正之機制,利用閘控振盪器技巧來解決初始相位之不確定性之外,同時能在數百個週期內迅速達到振盪器中心頻率之校正。
第二部份則提出一個用於低功率無線資料傳輸的四相位移鍵接收機,其有效應用了在注入鎖定振盪器中相位轉振幅變化的特性。相較於基於柯斯塔迴路或鎖相迴路解調器之高電路複雜度,此一基於注入鎖定之差動四相位移鍵解調器僅使用一個振盪器與一個振幅區別電路,如此便可大幅減少功率消耗及晶片面積。模擬結果則驗證了利用注入鎖定振盪器完成差動四相位移鍵解調之可行性。
zh_TW
dc.description.abstractPortable monitoring devices in the remote healthcare system require a low power solution both in biomedical signal acquisition and wireless data transmission for continuous long-term caring.
The first work presents an extremely low-power small-area VCO-based delta-sigma modulator (ΔƩM) for biomedical signal acquisition. The modulator nonlinearity induced by the VCO usually causes harmonic tones and deteriorates the SFDR/SNDR performance. This nonideal effect is mitigated by adopting the closed-loop architecture with 1-bit feedback. In addition, the signal swing at the VCO input is reduced to further suppress the nonlinearity. To maximize the operation range of the VCO-based ΔƩM and avoid signal distortion, the VCO center frequency should be an integer multiple of the sampling clock. An agile frequency calibration scheme is devised to correct the VCO free running frequency. The proposed calibration utilizes a gated VCO technique to remove the initial phase uncertainty and quickly correct the VCO center frequency in only hundreds of clock cycles.
The second part proposes an energy-efficient QPSK receiver for low-power wireless data transmission. It leverages the characteristic of phase-to-amplitude conversion possessed by the injection-locking oscillator. Compared to Costas-loop-based and PLL-based demodulators with high circuit complexity, the injection-locking-based D-QPSK demodulator exploits only one oscillator and one envelope discrimination circuit, which significantly reduces the power dissipation and chip area. Simulation results manifest the effectiveness of injection-locking technique for D-QPSK demodulation.
en
dc.description.provenanceMade available in DSpace on 2021-06-16T05:09:33Z (GMT). No. of bitstreams: 1
ntu-103-F90943005-1.pdf: 1920726 bytes, checksum: e2fe859d6df6b10c3ecd3bb1b6fb8c70 (MD5)
Previous issue date: 2014
en
dc.description.tableofcontentsChapter 1 Introduction 1
1.1 Motivation 1
1.2 Biomedical Signal Acquisition 2
1.3 Wireless Data Transmission 3
1.4 Thesis Overview 4
Chapter 2 VCO-Based Delta-Sigma ADC 5
2.1 Introduction 5
2.2 Low-Power ADC Architectures 5
2.2.1 SAR ADC 5
2.2.2 Delta-Sigma ADC 6
2.2.3 VCO-Based Delta-Sigma ADC 6
2.3 Operation Principle 7
2.4 Mathematical Interpretation 10
2.5 Resolution and SQNR for VCO-Based ADC 14
2.5.1 Resolution of Quantization Process 14
2.5.2 Theoretical SQNR Estimation 16
2.6 VCO Nonlinear Tuning Curve 17
2.7 Prior Works on VCO Linearity Enhancement 18
2.7.1 VCO-Based ADC with Digital Calibration 18
2.7.2 VCO-Based ADC with PWM Modulation 19
2.7.3 VCO-Based ADC with Swing Reduction 20
2.7.4 Closed-Loop VCO-Based Delta-Sigma ADC 21
Chapter 3 Low-Power VCO-Based ΔΣ Modulator Design with Single-Bit Feedback Architecture 23
3.1 Introduction 23
3.2 Proposed VCO-based Delta-Sigma Modulator 24
3.2.1 Modulator Architecture 24
3.2.2 Voltage Scaling 27
3.2.3 VCO-Based Delta-Sigma Modulator Implementation 28
3.2.4 Bulk-Controlled Inverter-Based Ring VCO 29
3.3 Frequency Calibration Based on Gated VCO Operation 31
3.3.1 Center Frequency Precision Requirement 31
3.3.2 Calibration Principle 34
3.3.3 Calibration Procedure 37
3.4 Design Considerations 38
3.4.1 VCO Phase Noise 38
3.4.2 Parasitic Capacitance 39
3.5 Measurement Results 41
Chapter 4 Low-Power ILO-Based QPSK Receiver Design 47
4.1 Introduction 47
4.2 QPSK Signaling 47
4.3 Conventional QPSK Receiver Architecture 49
4.3.1 Costas-Loop-Based Demodulation 49
4.3.2 PLL-Based Demodulation 50
4.4 Proposed ILO-Based QPSK Receiver Architecture 51
4.4.1 ILO Operation Principle 51
4.4.2 Prior ILO-Based Receivers 53
4.4.3 Proposed ILO-Based QPSK Receivers 55
4.5 Simulation Results and Discussions 58
Chapter 5 Conclusions and Future Works 63
5.1 Conclusions 63
5.2 Future Works 64
References 65
dc.language.isoen
dc.title應用於生醫系統之低功率基於壓控振盪器三角積分調變器與四相位移鍵接收機設計zh_TW
dc.titleDesign of a Low-Power VCO-Based Delta-Sigma Modulator and a QPSK Receiver for Biomedical Applicationsen
dc.typeThesis
dc.date.schoolyear102-2
dc.description.degree碩士
dc.contributor.coadvisor汪重光(Chorng-Kuang Wang)
dc.contributor.oralexamcommittee劉深淵(Shen-Iuan Liu),陳信樹(Hsin-Shu Chen),曾英哲
dc.subject.keyword壓控振盪器,三角積分調變器,頻率校正,四相位移鍵接收機,注入鎖定,zh_TW
dc.subject.keywordVCO,delta-sigma modulator,frequency calibration,QPSK receiver,injection locking,en
dc.relation.page70
dc.rights.note有償授權
dc.date.accepted2014-08-19
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
顯示於系所單位:電子工程學研究所

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