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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55467完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國 | |
| dc.contributor.author | Han-Wei Lu | en |
| dc.contributor.author | 呂涵薇 | zh_TW |
| dc.date.accessioned | 2021-06-16T04:04:05Z | - |
| dc.date.available | 2016-10-03 | |
| dc.date.copyright | 2014-10-03 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-10-02 | |
| dc.identifier.citation | [1] D. Kahng and M. M. Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” in IRE-AIEE Solid-State Device Res. Conf., (Carnegie Inst. Of Technol. Pittsburgh, PA), 1960.
[2] G. E. Moore, “Process in Digital Integrated Electronics,” in IEDM Tech. Dig., pp. 11-13, 1975. [3] The International Technology Roadmap for Semiconductors, 2013. [4] M. Depas, B. Vermeire, P. W. Mertens, R. L. Van Meirhaeghe, and M. M. Heyns., “Determination of Tunneling Parameters in Ultra-Thin Oxide Layer poly-Si/SiO2/Si Structures,” Solid-State Electronics, vol. 38, pp. 1465-1471, 1995. [5] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, ”Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's,” IEEE Electron Device Letters, vol. 18, pp. 209-211, 1997. [6] A. T. Fromhold, Quantum Mechanics for Applied Physics and Engineering, 1981. [7] E. Harari, “Dielectric Breakdown in Electrically Stressed Thin Films of Thermal SiO2,” J. Appl. Phys., vol. 49, pp. 2478-2489, 1978. [8] D. J. DiMaria, E. Cartier, and D. Arnold, “Impact Ionization, Trap Creation, Degradation, and Breakdown in Silicon Dioxide Films on Silicon,” J. Appl. Phys., vol. 73, pp. 3367-3384, 1993. [9] D. J. DiMaria and E. Cartier, “Mechanism for Stress-Induced Leakage Currents in Thin Silicon Dioxide Films,” J. Appl. Phys., vol. 78, pp. 3883-3894, 1995. [10] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Orier, M. Depas, P. J. Roussel, and H. E. Maes, “New Insights in the Relation between Electron Trap Generation and the Statistical Properties of Oxide Breakdown,” IEEE Trans. Electron Devices, vol. 45, pp. 904-911, 1998. [11] M. Houssa, and T. Nigam, “Model for the Current-Voltage Characteristics of Ultra-thin Oxide after Soft Breakdown,” J. Appl. Phys., vol. 84, pp. 4351-4355, 1998. [12] J. H. Stathis, “Percolation Models for Gate Oxide Breakdown,” J. Appl. Phys., vol. 86, pp. 5757-5766, 1999. [13] J. Cai and C. T. Sah, “Gate Tunneling Currents in Ultrathin Oxide Metal-Oxide-Silicon Transistors,” J. Appl. Phys., vol. 89, pp. 2272-2285, 2001. [14] M. Städele, B. R. Tuttle, and K. Hess, “Tunneling through Ultrathin SiO2 Gate Oxides from Microscopic Models,” J. Appl. Phys., vol. 89, pp. 348-363, 2001. [15] R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis, “Theory of Direct Tunneling Current in Metal-Oxide-Semiconductor Structures,” J. Appl. Phys., vol. 91, pp. 1400-1409, 2002. [16] F. Jiménez-Molinos, F. Gámiz, A. Palma, P. Cartujo, and J. A. López-Villanueva, “Direct and Trap-Assisted Elastic Tunneling through Ultrathin Gate Oxides,” J. Appl. Phys., vol. 91, pp. 5116-5124, 2002. [17] E. P. Nakhmedov, C. Radehaus, and K. Wieczorek, “Study of Direct Tunneling Current Oscillations in Ultrathin Gate Dielectrics,” J. Appl. Phys., vol. 97, pp. 064107-064107-7, 2005. [18] C. C. Lin and J. G. Hwu, “Investigation of Nonuniformity Phenomenon in Nanoscale SiO2 and High-k Gate Dielectrics”, J. Appl. Phys., vol. 112, pp. 064119-064119-5, 2012. [19] K. Takeuchi, A. Nishida, and T. Hiramoto, “Random Fluctuations in Scaled MOS Devices,” IEEE Simulation of Semiconductor Processes and Devices, SISPAD International Conference, pp.1-7, 2009. [20] C. C. Hong, W. R. Chen, and J. G. Hwu, “Local Thinning Induced Oxide Nonuniformity Effect on the Tunneling Current of Ultrathin Gate Oxide,” Jpn. J. Appl. Phys., vol. 41, pp. 1-4, 2002. [21] N. Yang, W. K. Henson, and J. J. Wortman, “Analysis of Tunneling Currents and Reliability of NMOSFETs with sub-2-nm Gate Oxides,” in IEDM Tech. Dig., pp. 453-456, 1999. [22] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” Journal of the Electrochemical Society, vol. 104, pp. 230-236, 1957. [23] V. Parkhutik, “New Effects in the Kinetics of the Electrochemical Oxidation of Silicon,” Electrochimica Acta, vol. 45, pp. 3249-3254, 2000. [24] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation,” Journal of Molecular Structure, pp. 607-610, 1999. [25] P. F. Schmidt, T. W. O’Keffe, J. Oroshnik, and A. E. Owen, “Doped Anodic Oxide Films for Device Fabrication in Silicon II. Diffusion Sources of Controlled Composition and Diffusion Results,” J. Electrochem. Soc., vol. 112, pp. 800-807, 1965. [26] G. C. Jain, A. Prasad, and B. C. Chakravarty, “Mechanism of the Anodic-Oxidation of Si at Constant Voltage,” J. Electrochem. Soc., vol. 126, pp. 89-92, 1979. [27] S. K. Sharma, B. C. Chakravarty, S. N. Singh, B. K. Das, D. C. Parashar, J. Rai, and P. K. Gupta, “Kinetics of Growth of Thin Anodic Oxides of Silicon at Constant Voltages,” J. Phys. Chem. Solids, vol. 50, pp. 679-684, 1989. [28] J. A. Bardwell, N. Draper, and P. Schmuki, “Growth and Characterization of Anodic Oxides on Si(100) Formed in 0.1 M Hydrochloric Acid,” J. Appl. Phys., vol. 79, pp. 8761-8769, 1996. [29] S. K. Ghanghi, VLSI Fabrication Principles, 2nd ed., (Wiley-Intersciencs), pp. 487-495, 1994. [30] S. M. Sze, Physics of Semiconductor Devices, (Wiley, New York), 1981. [31] K. J. Yang and C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, 1999. [32] K. Yang, Y. C. King, and C. Hu, “Quantum Effect in Oxide Thickness Determination from Capacitance Measurement,” in VLSI Symp. Tech. Dig., pp. 77-78, 1999. [33] R. Castagn and A. Vapaillé, “Description of the SiO2/Si Interface Properties by Means of Very Low Frequency MOS Capacitance Measurements,” Surf. Sci., vol. 28, pp. 157-193, 1971. [34] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley, New York), p. 331, 1982. [35] T. Suzuki, Y. Osaka, and M. Hirose, “Theoretical Interpretations of the Gap Amorphous Semiconductors,” Jpn. J. Appl. Phys., vol. 21, pp. L159-L161, 1982. [36] G. Fortunatoa and P. Migliorato, “Model for the Above-Threshold Characteristics and Threshold Voltage in Polycrystalline Silicon Transistors,” J. Appl. Phys., vol. 68, pp. 2463-2467, 1990. [37] C. A. Dimitriadis, N. A. Economou, and P. A. Coxon, “Field-Effect Conductance Activation-Energy in an Undoped Polycrystalline Silicon Thin-Film Trasistor,” Appl. Phys. Lett., vol. 59, pp. 172-174, 1991. [38] T. J. King, M. Hack, and I. W. Wu, “Effective Dendity-of-States Distributions for Accurate Modeling of Polycrystalline-Silicon Thin-Film Transistors,” J. Appl. Phys., vol. 75, pp. 908-913, 1994. [39] L. Colalongo, M. Valdinoci, A. Pellegrini, and M. Rudan, “Dynamic Modeling of Amorphous- and Polycrystalline-Silicon Devices,” IEEE Trans. Electron Devices, vol. 45, pp. 826-833, 1998. [40] M. Kimura, “Extraction Method of Trap Densities in TFTs Combining C-V and F-E Methods,” IEEE Electron Device Lett., vol. 33, pp. 845-847, 2012. [41] M. Kimura, K. T. Kojiri. A. Tanabe, and T. Kato, “Exact Extraction Method of Trap Densities at Insulator Interfaces using Quasi-Static Capacitance-Voltage Characteristics and Numerical Solutions of Physical Equations,” Solid-State Electron., vol. 69, pp. 38-42, 2012. [42] M. Kimura and Y. Hiroshima, “Evaluation of Thermal Annealing Before and After Formation of Gate Insulator Films by Extracting Trap Densities for SPC Poly-Si TFTs,” IEEE Electron Device Lett., vol. 34, pp. 256-258, 2013. [43] C. A. Dimitriadis, D. H. Tassis, N. A. Economou, and A. J. Lowe, “Determination of Bulk States and Interface States Distributions in Polycrystalline Silicon Thin-Film Transistors,” J. Appl. Phys., vol. 74, pp. 2919-2924, 1993. [44] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. I. Nakamura, M. Saito, and H. Iwai, “Prospects for Low-Power, High-Speed MPUs Using 1.5 nm Direct-Tunneling Gate Oxide MOSFETs,” Solid-State Electron., vol. 41, pp. 707-714, 1997. [45] A. Schenk and G. Heiser, “Modeling and Simulation of Tunneling through Ultra-Thin Gate Dielectrics,” J. Appl. Phys., vol. 81, pp. 7900-7908, 1997. [46] H. Y. Yang, H. Niimi, and G. Lucovsky, “Tunneling Currents through Ultrathin Oxide/Nitride Dual Layer Gate Dielectrics for Advanced Microelectronic Devices,” J. Appl. Phys., vol. 83, pp. 2327-2337, 1998. [47] L. F. Mao, C. H. Tan, and M. Z. Xu, “The Effect of Image Potential on Electron Transmission and Electric Current in the Direct Tunneling Regime of Ultra-Thin MOS Structures,” Microelectronics Reliability, vol. 41, pp. 927-931, 2001. [48] S. M. Sze, “Current Transport and Maximum Dielectric Strength of Silicon Nitride Films,” J. Appl. Phys., vol. 38, pp. 2951-2956, 1967. [49] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct Tunneling Hole Currents through Ulrathin Gate Oxides in Metal-Oxide-Semiconductor Devices,” J. Appl. Phys., vol. 91, pp. 258-264, 2002. [50] F. Mondon and S. Blonkowski, “Electrical Characterization and Reliability of HfO2 and Al2O3–HfO2 MIM Capacitors,” Microelectronics Reliability, vol. 43, pp. 1259-1266, 2003. [51] S. J. Ding, H. Hu, H. F. Lim, S. J. Kim, X. F. Yu, C. Zhu, M. F. Li, B. J. Cho, S. H. Chan, S. C. Rustagi, M. B. Yu, A. Chin, and D. L. Kwong, “High-Performance MIM Capacitor using ALD High-k HfO2-Al2O3 Laminate Dielectrics,” IEEE Electron Device Lett., vol. 24, pp. 730-732, 2003. [52] M. H. White and J. R. Cricchi, “Characterization of Thin-Oxide MNOS Memory Transistors,” IEEE Trans. Electron Devices, vol. 19, pp. 1280-1288, 1972. [53] S. K. Lai and D. R. Young, “Effects of Avalanche Injection of Electrons into Silicon Dioxide-Generation of Fast and Slow Interface States,” J. Appl. Phys., vol. 52, pp. 6231-6240, 1981. [54] Y. Nissan-Cohen, J. Shappir, and D. Frohman-Bentchkowsky, “Characterization of Simultaneous Bulk and Interface High-Field Trapping Effects in SiO2,” in IEDM Tech. Dig., pp.182-185, 1983. [55] V. G. Marathe, R. Paily, A. DasGupta, and N. DasGupta, “A Model to Study the Effect of Selective Anodic Oxidation on Ultrathin Gate Oxides,” IEEE Trans. Electron Devices, vol. 52, pp. 118-121, 2005. [56] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley, New York), p. 57, 1982. [57] Z. Chen and J. Guo, “Dramatic Reduction of Gate Leakage Current of Ultrathin Oxides through Oxide Structure Modification,” Solid-State Electronics, vol. 50, pp. 1004-1011, 2006. [58] Z. Chen, “Mechanism for Generation of the Phonon-Energy-Coupling Enhancement Effect for Ultrathin Oxides on Silicon,” Appl. Phys. Lett., vol. 91, pp. 223513-223513-3, 2007. [59] P. Ong and Z. Chen, “Evidence of enhanced phonon-energy coupling in SiO2/Si,” Appl. Phys. Lett., vol. 90, pp. 113516-113516-3, 2007. [60] R. Deaton and H. Z. Massoud, “Manufacturability of Rapid-Thermal Oxidation of Silicon: Oxide Thickness, Oxide Thickness Variation, and System Dependency,” IEEE Trans. Semiconductor Manufacture, vol. 5, pp. 347-357, 1992. [61] Y. Kotani and Y. Omura, “Analysis of Thin Oxide Growth Mechanisms in Partial-Pressure Rapid-Thermal Oxidation of Silicon,” J. Appl. Phys. Part 1, vol. 39, pp. 4549-4553, 2000. [62] Y. H. Wu, M. Y. Yang, A. Chin, W. J. Chen, and C. M. Kwei, “Electrical Characteristics of High Quality La2O3 Gate Dielectric with Equivalent Oxide Thickness of 5 Å,” IEEE Electron Device Letter, vol. 21, pp. 341-343, 2000. [63] D. Park, Y. C. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characteristics with Ta2O5 Gate Dielectric,” IEEE Electron Device Letter., vol.19, pp. 441-443, 1998. [64] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k Gate Dielectrics with Ultra-Low Leakage Current Based on Praseodymium Oxide,” in IEDM Tech. Dig., pp. 653-656, 2000. [65] Z. Chen, P. L. Ong, Y. Wang, and L. Han, “Lateral Heating of SiO2/Si: Interfacial Si Structure Change Causing Tunneling Current Reduction,” Appl. Phys. Lett., vol. 100, pp. 171602-171602-4, 2012. [66] S. Li, L. Han, and Z. Chen, “The Interfacial Quality of HfO2 on Silicon with Different Thicknesses of the Chemical Oxide Interfacial Layer,” Journal of the Electrochemical Society, vol. 157, pp. G221-G224, 2010. [67] L. F. Mao, Y. Tang, J. L. Wei, H. Zhang, M. Z. Xu, and C. H. Tan, “Effect of SiO2/Si interface roughness on gate current,” Microelectronics Reliability, vol. 41, pp. 1903-1907, 2001. [68] S. E. Tyaginov, M. I. Vexler, A. F. Shulekin, and I. V. Grekhov, “Statistical Analysis of Tunnel Currents in Scaled MOS Structures with a Non-Uniform Oxide Thickness Distribution,” Solid-State Electronics, vol. 49, pp. 1192-1197, 2005. [69] M. I. Vexler, S. E. Tyaginov, A. F. Shulekin, and I. V. Grekhov, “Current-Voltage Characteristics of Al/SiO2/p-Si MOS Tunnel Diodes with a Spatially Nonuniform Oxide Thickness,” Physics of Semiconductor Devices, vol. 40, pp. 1137-1143, 2006. [70] D. N. Pattanayak, J. G. Poksheva, R. W. Downing, and L. A. Akers, “Fringing Field-Effect in MOS Devices,” IEEE Trans. on Components, Hybrids, and Manufacturing Technology, vol. 5, pp. 127-131, 1982. [71] J. T. Liang, C. H. Shih, W. Chang, Y. X. Luo, M. K. Huang, N. D. Chien, W. F. Wu, S. M. Wu, C. Lien, R. Shirota, C. T. Huang, and S. Lu, A. Wang, “Impact of Edge Encroachment on Programming and Erasing Gate Current in NAND-Type Flash Memory,” IEEE Trans. Electron Devices, vol. 58, pp. 1257-1263, 2011. [72] C. H. Chen, K. C. Chuang, and J. G. Hwu, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors With Ultrathin Oxides and High-k Dielectrics,” IEEE Trans. Electron Devices, vol. 56, pp. 1262-1258, 2009. [73] C. W. Lee, “A Comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification,” M. S. thesis Dept. Elect. Eng, Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [74] R. Tsu and L. Esaki, “Tunneling in a Finite Superlattice,” Appl. Phys.Lett., vol. 22, pp.562-564, 1973. [75] H. C. Card and E. H. Rhoderick, “Studies of Tunnel MOS Diodes I. Interface Effects in Silicon Schottky Diodes,” J. Phys. D: Appl. Phys., vol. 4, pp. 1589-&, 1971. [76] S. Altindal, I. Dokme, M. M. Bulbul, N. Yalcin, and T. Serin, “The Role of the Interface Insulator Layer and Interface States on the Current-Transport Mechanism of Schottky Diodes in Wide Temperature Range,” Microelectron. Eng., vol. 83, pp. 499-505, 2006. [77] I. Dokme and S. Altindal, “On the Intersecting Behaviour of Experimental Forward Bias Current-Voltage (I-V) Characteristics of Al/SiO2/p-Si (MIS) Schottky Diodes at Low Temperatures,” Semicond. Sci. Technol., vol. 21, pp. 1053-1058, 2006. [78] D. A. Neamen, Semiconductor Physics and Devices, 3rd ed. (McGraw Hill), p. 339, 2003. [79] M. S. Liang, C. Chang, Y. T. Yeow, C. Hu, and R. W. Brodersen, “Creation and Termination of Substrate Deep Depletion in Thin Oxide MOS Capacitors by Charge Tunneling,” IEEE Electron Device Lett. vol. 4, pp. 350-352, 1983. [80] C. Y. Liu, B. Y. Chen, and T. Y. Tseng, “Deep Depletion Phenomenon of SrTiO3 Gate Dielectric Capacitor,” J. Appl. Phys. vol. 95, pp. 5602-5607, 2004. [81] W. Magnus and W. Schoenmaker, “Full Quantum Mechanical Model for the Charge Distribution and the Leakage Currents in Ultrathin Metal-Insulator-Semiconductor Capacitors,” J. Appl. Phys., vol. 88, pp. 5833-5842, 2000. [82] A. Ghetti, C. T. Liu, M. Mastrapasqua, and E. Sangiorgi, “Characterization of Tunneling Current in Ultra-Thin Gate Oxide,” Solid-State Electron, vol. 44, pp. 1523-1531, 2000. [83] M. Städele, B. R. Tuttle, and K. Hess, “Tunneling through Ultrathin SiO2 Gate Oxides from Microscopic Models,” J. Appl. Phys., vol. 89, pp. 348-363, 2001. [84] T. Ushiki, M. Yu, Y. Hirano, H. Shimada, M. Morita, and T. Ohmi, “Reliable Tantalum-Gate Fully-Depleted-SOI MOSFET Technology Featuring Low-Temperature Processing,” IEEE Trans. Electron Devices, vol. 44, pp. 1467-1472, 1997. [85] D. H. Lee, S. H. Joo, G. H. Lee, J. Moon, T. E. Shim, and J. G. Lee, “Characteristics of CMOSFETs with Sputter-Deposited W/TiN Stack Gate,” in VLSI Symp. Tech. Dig., pp. 119-120, 1995. [86] J. C. Hu, H. Yang, R. Kraft, A. L. P. Rotondaro, S. Hattangady, W. W. Lee, R. A. Chapman, C. P. Chao, A. Chatterjee, M. Hanratty, M. Rodder, and I. C. Chen, “Feasibility of Using W/TiN as Metal Gate for Conventional 0.13 μm CMOS Technology and Beyond,” in IEDM Tech. Dig., pp. 825-828, 1997. [87] K. Wafers and C. Misra, Oxides and Hydroxides of Aluminum, Alcoa Technical Report No. 19 Revised, Alcoa Laboratories, p. 64, 1987. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55467 | - |
| dc.description.abstract | 本篇論文主要探討p型與n型超薄閘極氧化層金氧半電容元件於累積區和深空乏區的電流穿隧行為。在論文的第二章中，我們發現，當p型矽基板的金氧半電容元件位於累積區時，元件的電流特性曲線有一個明顯的反曲點，我們合理的推斷此反曲點應該是跟位於閘極氧化層兩邊的金屬-半導體不對稱結構有關。經由理論公式搭配由實驗結果取得的數據來模擬得到了一個結論，反曲點就是元件從平能帶電壓慢慢進入累積區，矽基板的能帶彎曲到不能再彎曲，外加偏壓壓降開始幾乎只降在氧化層上的那個點，反曲點和氧化層厚度、介面特性和氧化層中的電荷量強烈相關。基於這個p型矽基板的金氧半電容元件之電流位於累積區會有一反曲點的原生特性，我們將其應用在超薄閘極氧化層厚度的萃取。而我們在n型矽基板的金氧半電容元件的順向偏壓區並沒有看到反曲點的現象，這是因為當元件偏壓在順向偏壓時，n型矽基板金氧半電容元件的能帶圖的方向都是一致的，都是在累積區。
在論文的第三章中，我們發現，p型與n型金氧半電容元件的電流特性曲線對閘極氧化層厚度的相依性是截然不同的，有趣的面積和周長相依特性在本章節中被提出。對於p型矽基板的金氧半電容元件而言，金屬和矽基板間的蕭基位障是不能被忽略的，但對於n型基板的金氧半電容元件而言，蕭基位障的影響較小。此外，邊際電場效應會使得p型基板的金氧半電容元件具有邊緣相關的電流特性，而n型基板的金氧半電容元件的電流則是與面積相關。 在論文的第四章中，我們設計三個不同厚度的正面鋁金屬閘極p型矽基板的金氧半電容元件來進一步研究元件的邊際不均勻現象。從電容和電流的特性曲線中發現，超薄的（＜4奈米）鋁金屬閘極元件的表現和較厚的鋁金屬閘極不太一樣，主要是因為元件會在位於超薄的鋁金屬閘極下方先進入深空乏區域，而元件邊際則還是在反轉區域，此時元件邊際可以提供電子去補充元件中心以維持電荷平衡，使得超薄鋁金屬閘極元件的空乏區電流會比較厚鋁金屬閘極元件增大許多，也就是說，邊際電場效應會加強元件的邊際電荷收集效率。 | zh_TW |
| dc.description.abstract | In this thesis, the current tunneling behaviors of MOS(p) and MOS(n) capacitors with ultra-thin SiO2 dielectric were explored under both accumulation and deep depletion modes. In Chapter 2, it is found that there is a clear “kinked point” in every I-V curve of MOS(p) capacitor under accumulation mode. It is reasonable to suspect that it is related to the unsymmetrical structure between the metal aluminum and substrate Si. By the theoretical simulation with the experimental results, it is concluded that the kinked voltage VG@|JG|’min is inferred to VG@EFS=EV but not VFB and are strongly dependent on oxide thickness, Dit, and Qeff/q. Based on the intrinsic kinked characteristic of I-V curve under accumulation region in MOS(p) devices, a further application to extract ultra-thin oxide thickness will be carried out. On the other hand, this kinked phenomenon does not appear in the forward positive bias J-V curve of MOS(n) capacitors. That is because there is no change of the direction of the band bending for MOS(n) capacitors in the forward bias.
In Chapter 3, it is found that the dependencies of I-V curves on gate oxide thickness for MOS(p) and MOS(n) capacitors are definitely different. Interesting area- and perimeter-dependent mechanisms of gate current are observed. The main issue is the Schottky barrier between metal and the silicon substrate could not be ignored for MOS(p) capacitors but would be less pronounced for MOS(n) capacitors. In addition, the effect of fringing field would further enhance the edge-dependent current conduction of MOS(p) capacitors. For MOS(n) capacitors, the current are area-dependent. In Chapter 4, to study this lateral non-uniformity phenomenon, three different thicknesses of top aluminum gate are intentionally designed to MOS(p) capacitors. According to C-V and I-V measurements carried out in the dark, it is found that the device with thin (< 4 nm) top Al-gate will result in entirely different electrical characteristics compared with the device with thick top Al-gate. It shows that the area beneath the probe enters deep depletion region earlier. And other areas which are still in inversion region will provide electrons to the gate center and therefore induce extra current in deep depletion region. That is, there is enhanced edge charge collection efficiency in inversion due to edge fringing field effect. Through this study, a thorough understanding of the basic characteristics of MOS(p) and MOS(n) capacitors could be achieved. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T04:04:05Z (GMT). No. of bitstreams: 1 ntu-103-F97943064-1.pdf: 6458360 bytes, checksum: f67490650f008089252451ed6b28dc60 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | Abstract (Chinese)……………………………………………………………………I
Abstract (English)…………………………………………………………………..III Contents………………………………………………………………………….…...V Table Caption…………………………………………………………………….....IX Figure Captions……………………………………………………………...…...…XI Chapter 1 Introduction………………………………………………………………1 1-1 Motivation…………………………………………………………………………1 1-2 Experimental Set-ups……………………………..……………………………….4 1-2-1 Anodization…………………………………………...…………………....4 1-2-2 Experimental Process……………………………………………………....6 1-3 Measurements……………………………………………………………………..7 1-3-1 Capacitance Correction……………………………...……………………..7 1-3-2 Extraction of Oxide Thickness.…………………………………………....8 1-3-3 Calculation of Interface Trap Density…...………………………………....9 1-4 Simulation Tools……...………….................……………………………………10 1-5 Summary…………………………………………………………………………10 Chapter 2 Comparisons of Current Tunneling Behavior for MOS(p) and MOS(n) Capacitors under Accumulation Mode….………………………...…...15 2-1 Introduction……………………………………………………………………....15 2-2 Experimental………………………………….………………………………….18 2-3 Results and Discussion…………………………………………………………..19 2-3-1 The Kinks for MOS(p) and No Kinks for MOS(n) Capacitors…………..19 2-3-2 The Concepts for the Kinks……………………………………………....21 2-3-3 Extraction of Dit@VFB, Qeff/q, and Qit(Ψs=0)/q……………..…………...23 2-3-4 Simulation Results of the Relationship between Ψs and Vox………...…...26 2-3-5 Application: Extraction of Ultra-thin Oxide Thickness...………………...31 2-4 Summary…………………………………………………………………………33 Chapter 3 Comparisons of Current Tunneling Behavior for MOS(p) and MOS(n) Capacitors under Deep Depletion Mode………………………………45 3-1 Introduction……………………………………………………………………...45 3-2 Experimental………………………………….………………………………….48 3-3 Results and Discussion…………………………………………………………..49 3-3-1 Dependencies of J-V Curves on Gate Oxide Thickness for MOS(p) and MOS(n) Capacitor…..………...……...……..……………………..……..49 3-3-2 Area- and Perimeter-Dependencies of J-V Curves.……………………....53 3-3-3 MOS(p) Capacitors under Deep Depletion Condition….………………...57 3-4 Summary…………………………………………………………………………58 Chapter 4 Comparisons of Current Tunneling Behavior for MOS(p) Capacitors with Different Top Al Gate Electrode Thickness…….…….………….69 4-1 Introduction……………………………………………………………………...69 4-2 Experimental………………………………….………………………………….71 4-3 Results and Discussion…………………………………………………………..72 4-3-1 AD and PD Phenomena in MOS(p) Capacitors with Different Top Al Gate Electrode Thicknesses………...……...……..……………………..……..72 4-3-2 Edge Charge Collection Efficiency Enhancement of 4 nm-Al Top Gate MOS(p) Capacitor under Deep Depletion Mode.……..………………....73 4-3-3 EDX and HRTEM Analyses in MOS(p) Capacitors with Different Top Al Gate Electrode Thickness………….……………………………...……...76 4-4 Summary…………………………………………………………………………77 Chapter 5 Conclusion & Future Works………………………….…….………….89 5-1 Conclusion.……………………….……………………………………………...89 5-2 Suggestions for Future Works…..…………….………………………………….91 References…………………………………………………………………………...93 Publication Lists…..……………………………………………………………….107 | |
| dc.language.iso | en | |
| dc.title | p型與n型超薄金氧半電容元件電流穿隧行為之比較與探討 | zh_TW |
| dc.title | Investigation of Current Tunneling Behavior for p- and n-type MOS Capacitors with Ultra-thin Oxides | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 林浩雄,李明逵,鄭晃忠,洪茂峰,吳幼麟 | |
| dc.subject.keyword | 電流穿隧行為,反曲點,面積/周長相依性,金氧半電容元件, | zh_TW |
| dc.subject.keyword | current tunneling behavior,kinked effect,area/perimeter dependencies,MOS capacitors, | en |
| dc.relation.page | 109 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-10-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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