以增進測試品質為目的之考慮壓降分佈的測試圖樣產生技術

Abstract

一般而言，在測試模式環境下，由於過多的轉換動作(switching activity)而導致耗能會比正常運作模式環境下來得高。我們必須盡可能地避免高耗能的發生，因為高耗能產生嚴重的壓降(IR drop)影響而造成邏輯閘的延遲時間增加，這樣的測試環境太嚴苛，這會使得一片好的晶片可能在經過測試時被判斷成有錯誤的晶片，導致過度測試(overkill)。 為了避免過度刪除情況發生，許多低耗能測試研究已經被提出來降低過高的轉換動作，但過度地降低轉換動作，有可能造成測試環境從嚴苛轉變為鬆散，而原本有錯誤的晶片可能在測試時被判斷為好的晶片，導致測試逃脫(test escape)。 本論文提出了考慮壓降分佈的測試圖樣產生技術，利用此技術能產生近似功能性圖樣的測試圖樣，使測試圖樣與功能性圖樣所造成的壓降分佈相似。實驗結果顯示利用此技術產生的測試圖樣，測試圖樣數量增加以及錯誤涵蓋率遺失都很小。

In general, power dissipation in test mode is higher than that in functional mode due to high switching activity. Severe IR drop caused by high power dissipation needs to be avoided because it may increase gate delay. Test environment with high power dissipation is too strict so that it may fail a good chip and then cause an overkill. Several low-power testing researches have been proposed to avoid from overkill by reducing switching activity. However, reducing too much switching activity may lead test environment to become loose. A test with loose environment may pass a faulty chip and then cause a test escape. This thesis proposed an IR drop aware test pattern generation technique. The functional-like test patterns generated with the proposed technique induced similar IR drop distributions to those induced by functional patterns. Experimental results showed that pattern count inflation, caused by applying the proposed technique, was very small, and had very low coverage loss.