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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Yi-Han Cheng | en |
| dc.contributor.author | 鄭伊涵 | zh_TW |
| dc.date.accessioned | 2021-06-16T03:55:51Z | - |
| dc.date.available | 2016-02-04 | |
| dc.date.copyright | 2015-02-04 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-12-17 | |
| dc.identifier.citation | [1] H.-R. Lee et al., 'A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18μm,' ISSCC Dig. Tech. Papers, pp. 2402-2411, Feb. 2006.
[2] B. Razavi, “The Role of PLLs in Future Wireline Transmitters,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 8, pp. 1786–1793, Aug. 2009. [3] A. N. Hafez and M. I. Elmasry, “A Fully-Integrated Low Phase-Noise Nested-Loop PLL for Frequency Synthesis,” IEEE Custom Integrated Circuits Conference, pp. 589-592, May. 2000. [4] Homayoun and Razavi, “Relationship Between Delay Line Phase Noise and Ring Oscillator Phase Noise,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 384-391, Feb. 2014. [5] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for Σ-∆ fractional-N frequency synthesizers allowing straightforward noise analysis,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp.1028-1038, Aug. 2002 [6] A. Homayoun and B. Razavi, “Analysis of phase noise in phase/frequency detectors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 3, pp. 529-539, Mar. 2013. [7] J. Lee and B. Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, Aug. 2000. [8] S.H. Cho, “Self-noise cancelling technique for voltage-controlled oscillators,” in Electronics Letters, vol. 44 , pp. 1436-1437, Dec. 2008. [9] P. L. Chen, C. C. Chung, J. N. Yang, and C. Y. Lee, “A Clock Generator with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-1285, Jun. 2006. [10] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankarads,“Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003. [11] J. Lin, B. Haroun, T. Foo, J.-S.Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, and J. Kirkpartick, “A PVT Tolerant 0.18 MHz to 600 MHz Self-Calibrated Digital PLL in 90 nm CMOS Process,” IEEE ISSCC Dig. Tech. Papers, pp. 488-489, Feb. 2004. [12] C.-C. Chung and C.-Y. Lee, “An All-digital Phased-Locked Loop for High-Speed Clock Generation,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55307 | - |
| dc.description.abstract | 本論文提出降低震盪器相位雜訊之頻率合成器。藉著開迴路延遲的相位雜訊小於閉迴路相位雜訊的特性，利用開迴路延遲改善環型振盪器的相位雜訊。提出的鎖相迴路能夠對高於頻寬的環形振盪器相位雜訊進行抑制。使用0.18μm製程，32k 赫茲的輸入訊號，輸出為1G赫茲的鎖相迴路在100k赫茲為-83dBc/Hz的相位雜訊，改善了10dB。此頻率合成器在1.8伏特供應電壓下消耗了17.64毫瓦。 | zh_TW |
| dc.description.abstract | A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillator. The proposed phase-locked loop (PLL) can suppress the noise beyond the PLL loop bandwidth. Fabricated in a 0.18μm CMOS technology, for a 32-kHz input frequency, the 1-GHz PLL with a ring oscillator can generate an output with the phase noise -83 dBc/Hz at a 100-kHz frequency offset, which is more than 10 dB suppression. The clock generator consumes 17.64 mW from a 1.8-V power supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T03:55:51Z (GMT). No. of bitstreams: 1 ntu-103-R01943014-1.pdf: 2424110 bytes, checksum: a9b503829ccd507900298b66f06199f3 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員審定書
誌謝 i 摘要 iii Abstract v Contents vii List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Basic Concepts of Phase-Locked Loop 3 2.1 PLL-based Frequency Synthesizers 3 2.2 Introduction 3 2.3 Phase Domain linear Model 4 2.4 Prior Arts 6 2.4.1 Cascaded PLLs 7 2.4.2 Nested PLLs 9 2.5 Summary 14 Chapter 3 Relationship between Delay Line Phase Noise and Ring Oscillator Phase Noise 15 3.1 Introduction 15 3.2 Phase Noise of Delay Lines 16 3.3 Phase Noise of Ring Oscillators 18 3.4 Comparison of Delay Lines and Ring Oscillators 22 3.5 Compact Phase Noise Equations 23 Chapter 4 Proposed Techniques for Suppressing Phase Noise 25 4.1 Fundamental Principle 25 4.2 Proposed Structure and Mathematical Model 27 4.3 Operation of the Proposed Structure 29 4.4 Design Considerations 32 4.4.1 N1 Value 33 4.4.2 Delay Line 36 4.4.3 CP Current 46 4.5 Summary 46 Chapter 5 Measurement Results 47 5.1 Chip Configuration 47 5.2 Experimental Results 49 5.3 Summary 53 Bibliography 55 Biography 59 Fig. 2-1. Phase-locked loop model 4 Fig. 2-2. Linear model of integer-N PLL. 4 Fig. 2-3. Cascaded PLLs. 7 Fig. 2-4. Linear model of cascaded PLLs. 8 Fig. 2-5. Nested PLLs. 9 Fig. 2-6. Linear model of nested PLLs. 10 Fig. 3-1. (a) Three-stage delay line with only one noisy inverter (b) Node voltages in response to a frequency equal to the oscillation frequency of a three-stage ring oscillator (c) Decomposition of the output voltage to an ideal noiseless square wave and a noise waveform (d) Approximation of the noise waveform in (c) to two uncorrelated weighted impulse trains 17 Fig. 3-2. (a) Three-stage ring oscillator retimed at t = 0 with only one noisy inverter (b) Jitter on all edges due to a single jitter event on V2 (c) Decomposition of V3 in (b) to an ideal noiseless square wave and a noise waveform, with g(t) serving as a “carrier” (d) Jitter on edges when inverter #2 adds jitter on every transition (e) Decomposition of V3 in (d) to an ideal noiseless square wave and a noise waveform. 20 Fig. 3-3. (a) Delay line and ring oscillator with one equivalent noise source, Vn1 . (b) Vn1 shown as a low-frequency component. 22 Fig. 4-1. Differential delay cell 25 Fig. 4-2. Closed-loop delay 26 Fig. 4-3. Opened-loop delay 26 Fig. 4-4. Phase noise of closed-loop delay and opened-loop delay 27 Fig. 4-5. Proposed VCO with self-noise cancellation 28 Fig. 4-6. Linear model of the proposed VCO with self-noise cancellation 28 Fig. 4-7. Linear model of the proposed VCO with self-noise cancellation 29 Fig. 4-8. Initial input for PFD1: (a) Unlocked condition. (b) Locked condition. 30 Fig. 4-9. Mechanism of controlled-voltage initialization 31 Fig. 4-10. Phase noise simulation with different N1 value 34 Fig. 4-11. Phase noise simulation with different N1 value with C2,1 ↑ 20% 34 Fig. 4-12. Phase noise simulation with different N1 value with C2,1 ↓ 20% 35 Fig. 4-13. Phase noise simulation with different N1 value with Icp,1 ↑ 20% 35 Fig. 4-14. Phase noise simulation with different N1 value with Icp,1 ↓ 20% 36 Fig. 4-15. Transfer function of VCO, ∆' and the sum. 38 Fig. 4-16. (a) Delay cell and its channel width size (b) Simulation result of phase noise and power under different transistor channel length 41 Fig. 4-17. Simulation result of phase noise and power under different transistor channel length at 60oC 42 Fig. 4-18. Simulation result of phase noise and power under different transistor channel length at 0oC 42 Fig. 4-19. Simulation result of phase noise and power under different transistor channel length when VDD=2V 43 Fig. 4-20. Simulation result of phase noise and power under different transistor channel length at VDD=1.6V 43 Fig. 4-21. Transient simulation result of signal before and after the delay line 44 Fig. 4-22. (a) The schematic of delay cell. (b) Phase noise of delay line. 45 Fig. 5-1. Chip configuration 47 Fig. 5-2. Chip photo 48 Fig. 5-3. PCB board 49 Fig. 5-4. Spectrum photo of (a) traditional PLL (b) proposed PLL 50 Fig. 5-5. Zoom-in Spectrum photo of (a) traditional PLL (b) proposed PLL 51 Fig. 5-6. Measured phase noise for the conventional and proposed PLL 52 Table 5-1 Performance comparisons 53 | |
| dc.language.iso | zh-TW | |
| dc.title | 降低具環形振盪器之鎖相迴路中相位雜訊的方法 | zh_TW |
| dc.title | A Phase Noise Suppression Technique for PLLs with Ring Oscillators | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),陳信樹,謝志成 | |
| dc.subject.keyword | 頻率合成器,鎖相迴路,相位雜訊,開迴路延遲,閉迴路延遲, | zh_TW |
| dc.subject.keyword | Frequency synthesizer,phase-locked loop,phase noise,opened-loop delay,closed-loop delay, | en |
| dc.relation.page | 57 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-12-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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