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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹 | |
dc.contributor.author | Tsung-Han Tsai | en |
dc.contributor.author | 蔡宗翰 | zh_TW |
dc.date.accessioned | 2021-06-16T03:51:57Z | - |
dc.date.available | 2020-01-30 | |
dc.date.copyright | 2015-01-30 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2015-01-15 | |
dc.identifier.citation | [1] M. S. W. Chen and R. W. Brodersen, “A subsampling UWB radio architecture by analytic signaling” Proc. ICASSP, May 2004, vol. 4, pp. 533–536.
[2] Z. Cao, S. Yan, and Y. Li, “A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 0.13um CMOS” ISSCC Dig. Tech. Paper, pp. 542–543, Feb., 2008 [3] C.-H. Chan, et al., 'A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure' IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 86- 87. [4] Hyeok-Ki Hong, et al., “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control” Proc. IEEE Custom Integr. Circuit Conf., San Jose, CA, Sep. 2012, pp. 1–4. [5] U.-F. Chio, et al., “Design and experimental verification of a power effective flash-SAR subranging ADC” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 8, pp. 607–611, Aug. 2010. [6] Y.-Z. Lin, et al., “A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS” IEEE Trans. Circuits Syst. Regul. Pap, vol. 60, no. 3, pp. 570-581, Mar. 2013. [7] C.-C. Liu, et al., “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13µm CMOS process” IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp.16-18. [8] C.-C. Liu, et al, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [9] Pieter J. A. Harpe et al., “A 0.47–1.6 mW 5-bit 0.5–1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios” IEEE J. Solid-State Circuits, VOL. 47, NO. 7, July 2012 [10] Dušan Stepanović et al., “A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS” IEEE J. Solid-State Circuits, VOL. 48, NO. 4, April 2013 [11] Kostas Doris et al., “A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS” IEEE J. Solid-State Circuits, VOL. 46, NO. 12, December 2011 [12] S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. [13] Tao Jiang, Wing Liu, Charlie Zhong, “A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC With improved feedback delay in 40-nm CMOS” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444-2453, Oct. 2012. [14] J. Guerber, et al., “A 10b Ternary SAR ADC with decision time quantization based redundancy” Asian Solid-State Circuits Conf., pp. 65-68, Nov. 2011. [15] Z. Boyacigiller, B. Weir, and P. Bradshaw, “An error-correcting 14b/20µs CMOS A/D converter” IEEE ISSCC Dig. Tech. Papers, Feb. 1981, pp. 62–63. [16] F. Kuttner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13µm CMOS” IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177. [17] S.-H. Cho, et al., “A 550-µW 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1881–1892, Aug. 2011. [18] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier” IEEE J. Solid-State Circuits, vol. 39, no. 7, Jul. 2004. [19] S. H. Lewis, et al., “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992. [20] A. M. Abo, P. R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999. [21] H.-Y. Tai, H.-W. Chen ,H.-S. Chen, ”A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS” IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 92-93. [22] L. Kull, et al., “A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced Speed in 32nm digital SOI CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 468–469. [23] V. Tripathi, and B. Murmann, “An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS” IEEE ESSCIRC Dig. Papers, Sep. 2013, pp.117-120 [24] W. Black and D. Hodges, “Time interleaved converter arrays” IEEE J. Solid-State Circuits, vol. SC-15, no. 6,pp. 1022-1029, Dec. 1980. [25] N. Kurosawa et al., “Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems” IEEE Trans. Circuits and Systems-Ⅰ, vol.48, no.3, pp.261-271, Mar. 2001. [26] Manar El-Chammas “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration” IEEE J. Solid-State Circuits, VOL. 46, NO. 4, April 2011 [27] Ku et al., “A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications” IEEE J. Solid-State Circuits, VOL. 47, NO. 8, August 2012 [28] C.-C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386-387. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55221 | - |
dc.description.abstract | 在高速類比數位轉換器研究中,提出了一個八位元每秒七億次取樣的連續漸進式類比至數位轉換器與一個七位元每秒二十四億次取樣的免校正時間交錯式的類比至數位轉換器被提出,皆是以40奈米CMOS設計。
在第一個設計中,為了避免比較器陷入亞穩態的狀況,採用了一個延遲轉移技術,把比較器的延遲轉換成類似於管線式類比數位轉換器裡的一點五位元的保護區間,並且加速了解析速度。這顆晶片在每秒7億次的轉換之下,功率消耗為5mW。在奈奎斯特的輸入頻率下有七位元的有效位元,其FoM為56 fJ/c.-s.。因為沒有使用額外的校正電路,此晶片的面積只有0.006mm2。 在第二個設計中,為了解決偏移電壓不匹配的問題,採用了一個偏移電壓補償演算法,把通到間偏移電壓的不匹配轉換成非線性度,再透過創造保護區間去補償。因此此時間交錯式的類比數位轉換器無須校正,在每秒二十四億次的轉換之下,功率消耗為14mW。在低頻輸入時FoM為130 fJ/c.-s.。 | zh_TW |
dc.description.abstract | In the field of high-speed ADC, an 8-bit 700MS/s single-channel SAR and 7-bit 2.4GS/s calibration-free time-interleaved ADC in 40nm CMOS are presented.
In the first design, in order to skip the comparator metastability, a delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range which is similar to pipelined ADC, and it also accelerates the comparison speed. This SAR ADC in 40nm CMOS technology achieves an ENOB of 7 in Nyquist and consumes 5mW. It results in a FoM of 56fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.006mm2. In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it, so no calibration is required. This time-interleaved ADC in 40nm CMOS technology achieves an ENOB of 5.4 with low-frequency input and consumes 14mW. It results in a FoM of 130fJ/conversion-step. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T03:51:57Z (GMT). No. of bitstreams: 1 ntu-103-R01943125-1.pdf: 2862717 bytes, checksum: a4eb991a8abbd7c01001fd3c3a2253e5 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 致謝 III
摘要 V Abstract VII Contents IX List of Figures XIII List of Tables XX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Analog to Digital Converter 4 2.1 Introduction 4 2.2 Performance Metrics 4 2.2.1 Offset and Gain Error 4 2.2.2 Differential and Integral Nonlinearity (DNL and INL) 5 2.2.3 Signal-to-Noise Ratio (SNR) 6 2.2.4 Total Harmonic Distortion (THD) 7 2.2.5 Spurious Free Dynamic Range (SFDR) 8 2.2.6 Signal to Noise and Distortion Ratio (SNDR) 8 2.2.7 Effective Number of Bits (ENOB) 8 2.2.8 Figure of Merit (FoM) 9 2.3 Architectures of Analog to Digital Converter 9 2.3.1 Flash ADC Architecture 10 2.3.2 Two-Step ADC Architecture 11 2.3.3 Pipelined ADC Architecture 12 2.3.4 Continuous-time Delta-sigma ADC Architecture 14 2.3.5 Successive-Approximation ADC Architecture 15 2.3.6 Time-Interleaved ADC 17 2.4 Summary 18 Chapter 3 Delay-shift SAR ADC 19 3.1 Introduction 19 3.2 Design Considerations for High-Speed SAR ADC 21 3.2.1 Comparison Time 22 3.2.2 DAC Settling Time 24 3.3 Proposed SAR ADC 25 3.3.1 Redundancy Range 26 3.3.2 Delay-Shift Technique 29 3.4 Benefits of Proposed Delay-Shift Technique 32 3.4.1 Comparison Time 32 3.4.2 DAC Settling Time 33 3.4.3 Dynamic Offset 34 3.5 Circuit Implementation 36 3.5.1 Clock Generator 36 3.5.2 Bootstrap 38 3.5.3 Capacitor Array 40 3.5.4 Comparator 42 3.5.5 SAR Logic 43 3.5.5.1 Digital Loop 43 3.5.5.2 Delay Line and Phase Detector 44 3.5.5.3 Digital Control Logic 46 3.6 ADC simulation Results 49 3.6.1 Algorithm Simulation 49 3.6.2 Transistor Level Simulation 50 3.7 Measurement Result 52 3.7.1 Measurement Setup 52 3.7.2 PCB Design 55 3.7.3 Floor Plan and Layout 59 3.7.4 Measurement Results 62 3.7.4.1 Static Performance 62 3.7.4.2 Dynamic Performance 63 3.8 Conclusions 66 Chapter 4 Calibration-Free Time-Interleaved SAR ADC 67 4.1 Introduction 67 4.2 Mismatches and Calibrations 68 4.2.1 Offset Mismatch and Calibrations 68 4.2.2 Gain Mismatch and Calibrations 71 4.2.3 Timing Skew Mismatch and Calibration 73 4.3 Proposed Calibration-Free Time-Interleaved ADC 77 4.3.1 Noise Analysis and Simulation with Mismatches 77 4.3.2 Proposed Architecture 80 4.3.2.1 Binary-Scaled Error Compensation 80 4.3.2.2 Offset-Compensation technique 82 4.3.2.3 Architecture 85 4.4 Circuit Implementation 90 4.4.1 Single Channel 90 4.4.1.1 Bootstrap 90 4.4.1.2 Capacitor Array 90 4.4.1.3 Comparator 91 4.4.1.4 SAR Logic 92 4.4.1.5 Source Follower 94 4.4.2 Global quantizer 96 4.4.2.1 Comparator 96 4.4.2.2 Global Logic 97 4.4.2.3 Feedback Signal Control 99 4.4.3 Clock Generator 102 4.5 Simulation Result 103 4.6 Measurements Result 106 4.6.1 Measurement Setup 106 4.6.2 PCB Design 107 4.6.3 Floor Plan and Layout 111 4.6.4 Measurement Results 114 4.7 Conclusions 119 Bibliography 122 | |
dc.language.iso | en | |
dc.title | 高速單通道與多通道連續漸進式類比至數位轉換器 | zh_TW |
dc.title | High-Speed Single Channel and Multi-Channel SAR ADC | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢,李泰成,蔡宗亨 | |
dc.subject.keyword | 類比至數位轉換器,連續漸進式,高速,低功率,時間交錯式,偏移電壓,無校正, | zh_TW |
dc.subject.keyword | analog to digital converter,SAR,high speed,low power,offset mismatch,time-interleaved,calibration-free, | en |
dc.relation.page | 125 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-01-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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