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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 資訊網路與多媒體研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55210
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor薛智文(Chih-Wen Hsueh)
dc.contributor.authorTang-Hsun Tuen
dc.contributor.author涂堂訓zh_TW
dc.date.accessioned2021-06-16T03:51:27Z-
dc.date.available2016-03-13
dc.date.copyright2015-03-13
dc.date.issued2015
dc.date.submitted2015-01-17
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55210-
dc.description.abstract在多核心系統上,使用多執行緒平行化的方式來加速應用程式的效能是一種相當常見的方法。然而,我們發現平行化不一定總是能帶來正向的加速效果,這是因為系統上存在著一些潛在的問題使得結果不如預期,像是執行緒間可觀的同步開銷及不合理的執行緒派發。研究人員常常會因為專注在平行化方法的設計上,而忽略了這些系統的問題。因此,我們提出一套系統化機制能在多核心系統上有效地加速應用程式。為了讓加速確實有效,整個機制的目標放在如何有系統地操作執行緒以妥善地使用這些多核心。我們將機制設計成三個階段來解決上述的系統問題,這包含了:如何將程式平行給執行緒執行、如何協調這些執行緒與系統核心、以及如何排程這些執行緒。為了讓機制更有彈性,每個階段採用獨立模組的設計,不僅能疊加在一起也可個別與其它既有的加速方法一同使用以達到更佳的加速效果。此外,我們也提供了相關的理論分析,包含了可行性及時間複雜度的分析,並在一台四核心的系統上做了一系列的實驗,以兩個不同類型的應用來驗證整個機制。實驗結果顯示我們的機制因為減少了系統上的開銷,與傳統的方法相比能達到更好的效能。zh_TW
dc.description.abstractIn multi-core environment, parallelizing with multi-hreading is a common approach to speed up application programs. However, we find that the parallelization efforts might not always lead to positive performance gain because of some potential system issues, such as the significant synchronization overhead among threads and the unreasonable dispatching of threads. Researches focusing on the parallelization of specific program components without consideration of the entire system might often overlook these system issues. Therefore, we propose to design a systematic mechanism to speed up application programs effectively on multi-core systems. To make the speed-up effective, the mechanism aims at how to manipulate threads to utilize multiple cores systematically. It includes three phases: parallelizing the program into threads, coordinating these threads with system kernel, and scheduling these threads, to solve the problem with consideration of the system issues. For the flexibility, each phase is developed as an independent module, and can be applied not only all together but also individually with other existing speed-up approaches to achieve higher performance. Furthermore, we also provide related theoretical analysis including feasibility and time complexity, and conduct a series of experiments with two different kinds of applications to verify the mechanism on a 4-core machine. The results show that it can deliver higher performance than traditional approaches because of the reduction of the system overhead.en
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Previous issue date: 2015
en
dc.description.tableofcontents1 Introduction 1
2 Background 14
2.1 H.264 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.1 Dependency Analysis in H.264 . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 Parallelization of Deblocking Filter . . . . . . . . . . . . . . . . . . . . . 17
2.2 idSVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Dependency Analysis in idSVM . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Thread Anomalies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 T-L er Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 PG and PCG Scheduling Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 25
3 A Systematic Speed-Up Mechanism 26
3.1 Phase I: Parallelizing a Program into Threads . . . . . . . . . . . . . . . . . . . 28
3.1.1 Batch-Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.1.1 Considering Programs . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.1.2 Design of Pipelining Stages . . . . . . . . . . . . . . . . . . . . 32
3.1.1.3 Design of Batch-Pipelining . . . . . . . . . . . . . . . . . . . . . 35
3.1.1.4 BP Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.1.5 Optimized Allocation of Sub-Jobs . . . . . . . . . . . . . . . . . 40
3.1.2 Software Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 Phase II: Coordinating Threads with System Kernel . . . . . . . . . . . . . . . . 46
3.2.1 User Dispatching Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.1.1 UDispatch Architecture . . . . . . . . . . . . . . . . . . . . . . 47
3.2.1.2 Comparison with Other Mechanisms . . . . . . . . . . . . . . . 49
3.2.2 UDispatch + Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.3 Unified UDispatch Framework . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 Phase III: Scheduling Threads to Cores . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.1 One-to-One Mapping Scheduling Algorithm (1-1) . . . . . . . . . . . . . 58
3.3.2 Greedy Scheduling Algorithm (GD) . . . . . . . . . . . . . . . . . . . . . 60
3.3.3 Overrun Removal Scheduling Algorithm (oPG and oPCG) . . . . . . . . 62
3.3.3.1 System Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.3.3.2 Algorithm Design . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.3.3 Practical Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4 sSpeedUp Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.1 H.264 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.1.1 Annealing Procedure on H.264 Decoder . . . . . . . . . . . . . 80
3.4.1.2 Optimization on H.264 Decoder . . . . . . . . . . . . . . . . . . 81
3.4.2 idSVM Learning Application . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.4.3 Other Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4 Experiment Results 87
4.1 H.264 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.1 An Unoptimized H.264 Decoder . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.2 An Optimized H.264 Decoder . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1.3 Analysis of Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2 idSVM Learning Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.1 Analysis of Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.2 Analysis of Scheduling Algorithms . . . . . . . . . . . . . . . . . . . . . . 102
5 Conclusion 108
Current Publication Lists 110
Bibliography 113
dc.language.isoen
dc.subject多核心zh_TW
dc.subject排程zh_TW
dc.subject系統化zh_TW
dc.subject平行化zh_TW
dc.subject執行緒zh_TW
dc.subjectThreaden
dc.subjectSystematicen
dc.subjectMulti-coreen
dc.subjectParallelizationen
dc.subjectSchedulingen
dc.title一套系統化的多核心系統加速機制zh_TW
dc.titleA Systematic Speed-Up Mechanism for Multi-Core Systemsen
dc.typeThesis
dc.date.schoolyear103-1
dc.description.degree博士
dc.contributor.oralexamcommittee吳家麟(Ja-Ling Wu),郭大維(Tei-Wei Kuo),施吉昇(Chi-Sheng Shih),徐讚昇(Tsan-sheng Hsu),張榮貴(Rong-Guey Chang)
dc.subject.keyword多核心,系統化,平行化,執行緒,排程,zh_TW
dc.subject.keywordMulti-core,Systematic,Parallelization,Thread,Scheduling,en
dc.relation.page121
dc.rights.note有償授權
dc.date.accepted2015-01-17
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept資訊網路與多媒體研究所zh_TW
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