三維架構之雙輻射狀功率合成技術之研究

Abstract

本篇論文主要是討論與發展可應用於晶片內的功率結合技術。本篇論文首先提出一個創新的三維架構之雙輻射狀功率放大器架構。這個架構提供了在阻抗選擇上的自由度。這個架構的概念可以突破目前都是二維功率結合技術的瓶頸，這架構可以在不用妥協的情況下同時達到電路佈局得對稱性並且可以達到所小晶片面積的優點。藉由使用所提出的功率放大器架構，在一個晶片面積內可以同時實現功率分配器與功率結合器的設計，因此可以達到縮小晶片面積的目的。這個架構所擁有的阻抗選擇自由度使得它能不受限操作頻率的限制而可應用於不同頻帶的設計。為了驗證這個創新的架構的可行性，我們針對不同的頻帶設計了許多三維功率放大器，並且也在不同的CMOS製程來驗證架構的可行性。 以應用於毫米波功率放大器而言，我們將三維功率放大器分別在不同的製程設計了應用在60GHz的頻帶上設計了結合四路功率放大器與八路的功率放大器。這二個功率放大器皆可以達到高輸出功率並且擁有高的單位輸出功率密度。其中60GHz的四路結合的功率放大器也是第一個在毫米波頻段上具有多模操作所需要的阻抗補償機制的設計。另一個八路功率結合的功率放大器更是目前利用CMOS技術可以達到23 dBm最大的輸出功率的設計，並且面積只有0.72平方毫米。 關於三維功率放大器在微波頻段的應用，我們也提出一個蝶型領結式的雙輻射狀功率放大器架構。這個架構主要是用來抑制雙輻射功率放大器架構中二個輻射網路中間存在的寄生電容可能造成回授的現象以致於會有穩定的問題。這樣的架構也同時實現於24-GHz與5-GHz的應用。其中24-GH的四路功率結合放大器更可輸出目前CMOS最高的輸出功率，可達到26.1 dBm的輸出並且具有非常高的單位面積可生產的功率密度，可達到635 mW/mm2。另外，實現於5-GHz的三維功率放大器分別可達到0.5瓦以及接近1瓦的輸出功率。 在論文的最後，我們提出一個改善IM3的線性化技術，這個技術實現於一個60-GHz的功率放大器。量測結果顯示IM3可以改善超過30 dBc的效果並且驗證在60-GHz應用中涵蓋7 GHz頻寬的四個頻道皆可以發揮效果。藉由這樣預失真的效果，輸出的OP1dB在四個頻道皆可以因此提高一倍的輸出功率。

The research on the development of on-chip power combining techniques is presented this dissertation. For the first time, an innovative 3-D dual-radial PA architecture is proposed. It provides design freedom of impedance selection of power device in TF-based mm-wave PA design. This idea also makes distinguished breakthrough to the traditional 2-D PA architecture without compromising symmetry and compact size of layout. This technique presents not only a power combiner but a new PA architecture. By taking advantage of the dual-radial architecture, the power splitting network and power combining network can share the same active area to complete the fully integration with symmetry layout. This new technique also possesses the impedance freedom to make its feasibility from mm-wave frequency band to microwave frequency band. To demonstrates the feasibility of the proposed 3-D dual-radial PA architecture. Various 3-D PAs have been successfully implemented in different frequency application and in different CMOS process. In terms of mm-wave 3-D PA, a 4-way 60-GHz 3-D PA and 8-way balanced 3-D PA are demonstrated not only the high output power but also high PAD performance. The 4-way 60-GHz PA is also the first mm-wave PA equipped with impedance compensation mechanism for multi-power operation. The 8-way balanced 3-D PA demonstrates the highest 60-GHz output power of 23 dBm in CMOS technology. The chip area of 8-way 60-GHz PA is only 0.72 mm2. In terms of microwave 3-D PA, a bowtie dual-radial architecture is proposed to mitigate the inherent feedback capacitor existing in the original dual-radial PA architecture for unconditional stability consideration. This idea is realized in 24-GHz and 5-GHz PA. The 4-way 3-D bowtie radial PA can achieves highest Pout of 26.1 dBm and high PAD of 635 mW/mm2. Furthermore, the proposed 3-D PA architecture is also adopted to implement a half-watt and one-watt 5-GHz PA in 180-nm CMOS. The proposed fully integrated 5-GHz PA can achieve Pout of 29.5 dBm in cost effective 180-nm CMOS with only 3.33 mm2. A 60-GHz power amplifier utilizing the pre-distortion linearizer was demonstrated at last. The proposed linearization technique can significantly improve IMD3 distortion over 30 dBc at 60-GHz. This technique is valid to cover the wide bandwidth form 57 GHz to 66 GHz. The performances of IP1dB of the 60-GHz PA can be extended around 7 dB and the corresponding OP1dB can be boosted 3 dB in average by enabling the proposed linearization technique.