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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Cheng-Yu Han | en |
| dc.contributor.author | 韓承佑 | zh_TW |
| dc.date.accessioned | 2021-06-16T02:28:11Z | - |
| dc.date.available | 2015-08-06 | |
| dc.date.copyright | 2015-08-06 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-03 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53716 | - |
| dc.description.abstract | 本論文提出一個新穎的想法去修改測試向量為了減少在捕獲造成電源供應雜訊太大之測試向量，由於此種測試向量會造成過長的路徑延遲，當路徑延遲大於電路時脈，會造成良好的晶片測試失敗。我們計算因為電源雜訊而產生的路徑延遲，我們的演算法精準度與HSPICE比較，只有8%之誤差；速度與NANOSIM比較，在大型電路中可以加速272倍。實驗結果顯示，我們在大型電路中成功辨識出88個測試向量有過長的路徑延遲，並且利用業界測試向量產生器重新產生安全的測試資料。我們提出的技術相對於考慮功率的自動測試向量產生器有較短的測試向量、較低的電壓降、較高的錯誤涵蓋率。 | zh_TW |
| dc.description.abstract | This thesis propose a power-supply-noise-aware test pattern analysis and regeneration framework. The proposed framework analysis timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear analytical functions, instead of solving nonlinear functions. Moreover, the function is technology dependent, so there is no need to perform spice characterization for each cells. The experimental results show, for small circuits, the error is less than 5% compared with HSPICE. For large circuits, we achieved 272 times speed up compared with NANOSIM. We perform timing analysis on a 638K gate benchmark circuit to identify 88 timing-violation test patterns (out of 31K test patterns) that are difficult to detect by traditional techniques. After test pattern regeneration, we removed all risky patterns, without fault coverage loss and with only little test inflation. The proposed technique generates shorter test sets and higher fault coverage than commercial power-aware ATPG. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T02:28:11Z (GMT). No. of bitstreams: 1 ntu-104-R02943141-1.pdf: 1378311 bytes, checksum: 5b0481029f7abdee67c17b0846f01d7a (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 中文摘要 i
ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES vi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 6 1.3 Contributions 10 1.4 Organization 11 Chapter 2 Background 12 2.1 Prior work in low power testing 13 2.2 PSN aware Timing Analysis 18 2.3 Extra Gate Delay Calculation 21 Chapter 3 Purposed Techniques 24 3.1 Overall Flow 25 3.2 Charge Model 28 3.3 Extra Gate Delay Estimation 31 3.3.1 Nominal Voltage Delay calculation 36 3.3.2 Near Threshold Voltage Delay Calculation 37 3.4 Window Partition 39 3.5 Test Pattern Regeneration 41 Chapter 4 Experimental Result 43 4.1 Experimental Setup 43 4.2 Path Delay Estimation 45 4.3 Risky Pattern Identification 48 4.4 Path Delay Consider VDD Scaling and VT Variation 49 4.5 Compare with power-aware ATPG 51 Chapter 5 Conclusion and Future Work 53 Reference 55 | |
| dc.language.iso | en | |
| dc.title | 考慮電源雜訊之測試資料分析與重建用於增進良率之方法 | zh_TW |
| dc.title | Power-Supply-Noise-Aware Test Pattern Analysis and Regeneration for Yield Improvement | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),黃錫瑜(Shi-Yu Huang) | |
| dc.subject.keyword | 電源雜訊,測試,時序分析,良率, | zh_TW |
| dc.subject.keyword | power-supply-noise,PSN,testing,transition fault,yield,timing analysis, | en |
| dc.relation.page | 66 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2015-08-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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