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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Cheng-Hao Luo | en |
dc.contributor.author | 羅晟豪 | zh_TW |
dc.date.accessioned | 2021-06-16T02:27:16Z | - |
dc.date.available | 2020-08-07 | |
dc.date.copyright | 2015-08-07 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-04 | |
dc.identifier.citation | [1] B. Hargreaves, H. Hult, and S. Reda, 'Within-Die Process Variations: How Accurately Can They Be Statistically Modeled?' Design Automation Conference, pp. 524-530, Mar. 2008.
[2] Overclockers.com website, http://www.overclockers.com, 2015. [3] T. Austin, V. Bertacco, D. Blaauw, and T. Mudge, 'Opportunities and Challenges for Better Than Worst-Case Design,' 10th Asia and South Pacific Design Automation Conference, vol. 1, pp. I-2 - I-7, Jan. 2005. [4] D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, “Razor: A Low-Power Pipeline Based on Circuit Level Timing Speculation,” IEEE/ACM International Symposium on MICRO, pp. 7-18, Dec. 2003. [5] S. Das, C. Tokunaga, S. Pant, W.H. Ma, S. Kalaiselvan, K. Lai, D.M. Bull, and D. Blaauw, 'RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance,' IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 32-48, Jan. 2009. [6] S. Narayanan, J. Sartori, R. Kumar, and D.L. Jones, 'Scalable Stochastic Processors,' Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 335-338, Mar. 2010. [7] ARM, ARM1136JF-STM and ARM1136J-STM Revision: r1p5 Technical Reference Manual, 2009 ARM Limited, ARM DDI 0211K. [8] ARM, ARM Architecture Reference Manual, 2005 ARM Limited, ARM DDI 0100l. [9] A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, and V. Pokala, 'A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor,' IEEE International Solid-State Circuits Conference, pp. 398-399, Feb. 2007. [10] S. Das, G.S. Dasika, K. Shivashankar, and D. Bull, 'A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation,' IEEE Transactions on Circuits and Systems, vol. 61, no. 8, pp. 2290-2298, Aug. 2014. [11] M. Fojtik, D. Fick, K. Yejoong, N. Pinckney, D. Harris, D. Blaauw, and D. Sylvester, 'Bubble Razor: An Architecture-Independent Approach to Timing-Error Detection and Correction,' IEEE International Solid-State Circuits Conference, pp. 488-490, Feb. 2012. [12] B. Stackhouse, S. Bhimji, C. Bostak, D. Bradley, B. Cherkauer, J. Desai, E. Francom, M. Gowan, P. Gronowski, D. Krueger, C. Morganti, and S. Troyer, 'A 65 nm 2-Billion Transistor Quad-Core Itanium Processor,' IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 18-31, Jan. 2009. [13] K.A. Bowman, J.W. Tschanz, N.S. Kim, J.C. Lee, C.B. Wilkerson, S.L. Lu, T. Karnik, and V.K. De, 'Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance,' IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 49-63, Jan. 2009. [14] A.B. Kahng, S. Kang, R. Kumar, and J. Sartori, 'Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 3, pp. 404-417, Mar. 2012. [15] B. Greskamp, L. Wan, U.R. Karpuzcu, J.J. Cook, J. Torrellas, D. Chen, and C. Zilles, 'Blueshift: Designing Processors for Timing Speculation from the Ground Up,' IEEE 15th International Symposium on High Performance Computer Architecture, pp. 213-224, Feb. 2009. [16] Han-Zhang Wang, “Design and Implementation of a Stochastic ARM Core with Circuit Level Recovery Mechanism,” Master Thesis, NTU GIEE, 2014. [17] TSMC, TSMC 90nm CLN90G Process SAGE-XTM v3.0 Standard Cell Library Databook, Mrach 2005, Release 1.1. [18] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, 'MiBench: A Free, Commercially Representative Embedded Benchmark Suite,' IEEE International Workshop on Workload Characterization, pp. 3-14, Dec. 2001. [19] SimpleScalar Version 4.0 Test Releases Website, http://www.simplescalar.com/v4test.html, 2015. [20] D. Bull, S. Das, K. Shivashankar, G.S. Dasika, K. Flautner, and D. Blaauw, 'A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation,' IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp. 18-31, Jan. 2011. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53668 | - |
dc.description.abstract | 傳統的數位設計需要保證電路能夠於最壞的情況下(worst case)仍然能夠不發生錯誤。可能造成錯誤發生的原因來自於各種設計不確定性(design uncertainty),如製程、電壓、溫度的變異。隨著製程的進步以及對於效能的追求,設計不確定性對於晶片設計的影響逐漸提升。在使用先進製程時,設計者往往需要留下大量的設計邊界(design margin)來提高整體設計的良率,造成設計成本的浪費。因此,各種設計邊界消除的技術相繼被提出以提升效能並減少浪費,錯誤容忍技術為其中一個直接且極為有效的方式。藉由加入偵測與回復錯誤的機制到設計中,保留的邊界值能夠完全被消除,得到較最壞情況更佳(better-than-worst-case)的設計,其具有對抗設計不確定性的能力,更增加整體設計的可靠度(reliability)。
本論文在ARM處理器上設計並實現一錯誤偵測與回復的機制,使其能夠有效對抗各種變異並達到更高的效率與可靠度。我們基於Razor與Surger建立一混合式的錯誤偵測機制,結合全域與區域的時序(timing)資訊做錯誤的偵測。基於指令的重播(instruction replay)在架構層級實現錯誤回復的機制,輔以頻率調控機制以避免重複的錯誤導致死結(deadlock)產生。此外,為使錯誤容忍機制能夠更有效率的運作,我們將可能發生的時序錯誤納入考量,以電路的路徑活躍度(path activation probability)對設計進行優化,使其錯誤率降低以提高效率。我們提出一系統性的完整方案將錯誤容忍機制融入處理器的設計中,達到消除設計邊界的目的。 | zh_TW |
dc.description.abstract | With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. The operating point is chosen under a worst-case scenario of variations for the circuit to operate correctly. This design methodology is the so called worst-case design. On the other hand, it is possible to reduce the design margins if timing error is detectable and recoverable, which leads to prominent energy saving and better reliability compared with the worst-case design.
In this Thesis, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant design margins and implement it on an ARM microprocessor. We build a hybrid error detection mechanism that combines global and local timing information to detect errors. The error correction mechanism is implemented on architectural-level based on instruction replay, and a frequency control mechanism is added to prevent possible deadlock situation caused by repeated errors. To better utilize the underlying error-tolerance mechanism, an activity-driven optimization procedure is proposed to reshape the slack distribution based on path activity. As a result, the design becomes more robust against process, voltage, and temperature variations. On the other hand, the power efficiency increases due to the reduction of design margins, thus making it a better-than-worst-case design. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T02:27:16Z (GMT). No. of bitstreams: 1 ntu-104-R02943048-1.pdf: 2266679 bytes, checksum: f20b2f33937030a6b8aef25911e9e13d (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 第一章 簡介 伍
第二章 設計邊界消除技術 陸 第三章 架構與實現 柒 第四章 實驗結果 捌 第五章 結論 玖 ABSTRACT i LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Rising Design Uncertainties 1 1.2 Better-Than-Worst-Case Design 3 1.3 Stochastic Processor 4 1.4 ARM1136 5 1.4.1 Architecture 5 1.4.2 Instruction Set 7 1.4.3 Register Bank 8 1.5 Motivation 9 1.6 Thesis Organization 10 CHAPTER 2 DESIGN MARGINS ELIMINATION TECHNIQUES 11 2.1 Look-Up Table Based Approach 11 2.2 Canary-Circuit Based Approach 12 2.3 Error-Tolerant Approach 13 2.3.1 Razor Overview 13 2.3.2 Error Detection Scheme 14 2.3.3 Error Correction Scheme 17 2.3.4 System Timing 18 CHAPTER 3 PROPOSED ARCHITECTURE AND IMPLEMENTATION 21 3.1 System Architecture 21 3.2 Activity-Driven Optimization 23 3.3 Error Detection 26 3.4 Latch-Based Solution to Short-Path Constraint 30 3.5 Error Correction 33 CHAPTER 4 EXPERIMENTAL RESULTS 37 4.1 Design Flow 37 4.2 Evaluation Results 38 4.2.1 Activity-Driven Optimization 39 4.2.2 Latch-Based Solution to Short-Path Constraint 44 4.3 Implementation Results 47 4.4 Simulation Results 51 4.5 Testing Consideration 56 4.6 Measurement Results 57 4.7 Comparison 59 CHAPTER 5 CONCLUSION 61 REFERENCE 63 | |
dc.language.iso | en | |
dc.title | ARM1136的時序錯誤偵測與更正機制之設計與實作 | zh_TW |
dc.title | Design and Implementation of a Timing-Error Detection and Correction Mechanism on ARM1136 | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 游竹(Chu Yu),吳安宇(An-Yeu Wu),林伯星(Bor-Shing Lin) | |
dc.subject.keyword | 設計邊界消除,錯誤偵測,錯誤回復, | zh_TW |
dc.subject.keyword | Design Margins Elimination,Error Detection,Error Correction, | en |
dc.relation.page | 65 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-04 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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