全CMOS輔助單點溫度校正之低溫度飄移參考電壓設計

Abstract

在一個積體電路系統中，往往需要參考電壓，以負責提供一個穩定的電壓值，而此電壓值理想上不隨著溫度、供應電壓及製程變異而改變；在類比電路的應用中，扮演著不可或缺的角色。 本論文中提出一個全CMOS輔助單點溫度校正的參考電壓，可在0.8伏特的電源供應下運作。傳統的參考電壓，是以BJT做為核心元件來實現；但一個BJT需佔去0.75伏特以上的跨壓；因此，在先進製程的供壓不斷降低的趨勢下，採用BJT的架構漸漸不適合做為電路實現的方式。而全CMOS的電路架構雖然可解決此問題，但由於MOS本身較差的溫度特性，往往需要更為複雜的校正技術，才能得到較低的溫度係數。在本論文中的架構中，直接對偏壓電流進行室溫校正，以穩定MOS的溫度特性；因此可以在全MOS的電路組態底下，以簡單的校正流程，即可得到低溫度飄移的輸出電壓。 此參考電壓以台積電40奈米的製程設計；電路可在0.8伏特的供壓下操作，面積為0.049 mm2。總量測樣本為8顆，量測溫度範圍為 -10 ˚C ~ 100 ˚C；而量測結果顯示：平均的溫度係數約為30 ppm/˚C，三個標準差的電壓飄移僅為0.14 %，低頻的電源拒絕比為 -48 dB，且供壓敏感度小於1.8 %/V。

Voltage reference (VR) is required in integrated circuits for providing a stable voltage, which is ideally immune to temperature, supply and process variations. It undoubtedly plays a crucial role in analog circuit applications. This thesis proposes an all-CMOS voltage reference with assisted-one-temperature -point trim in a 40-nm CMOS technology that is functional from 0.8-V supply. Conventionally, BJT-based references are commonly used, but a BJT consumes at least 0.75V headroom. Thus, they are not suitable for advanced technologies because of supply scaling. Previously solutions include BJT-free designs, but they exhibit worse temperature characteristics, or complex trimming methodology is demanded to achieve a reasonable temperature coefficient (TC). In this work, one-temperature-point trim on bias makes MOS exhibit better temperature characteristics. Thus, an all-MOS circuit topology featuring low temperature drift can be achieved with simple trimming procedures. The chip is fabricated in a TSMC 40-nm CMOS technology. It works down to a supply of 0.8 V and occupies 0.049 mm2. Total 8 samples was measured from -10˚C to 100 ˚C. Measurement results show that the average TC is about 30 ppm/˚C and 3σ spread is only 0.14 %. Also, PSR of -48 dB at a low frequency is attained, and line sensitivity (LS) is below 1.8 %/V.