請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53041
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維 | |
dc.contributor.author | Xiang-Zhi Huang | en |
dc.contributor.author | 黃祥智 | zh_TW |
dc.date.accessioned | 2021-06-15T16:40:48Z | - |
dc.date.available | 2015-08-20 | |
dc.date.copyright | 2015-08-20 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-11 | |
dc.identifier.citation | [1] Mengying Zhao , Yuan Xue, Xue.C.j, Minimizing MLC PCM Write Energy for Free through Profiling-based State Remapping, ASP-DAC 2015.
[2] Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie, Energy-Efficient Multi-Level Cell Phase-Change Memory System with Data Encoding, ICCD 2011. [3] Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel Loh, and Doug Burger, Preventing PCM Banks from Seizing Too Much Power, MICRO 2011. [4] Jianhui Yue, Yifeng Zhu, Exploiting Subarrays Inside a Bank to Improve Phase Change Memory Performance, DATE 2013. Problem in File Systems. ACM Transactions on Computer Systems, 2000. [5] Ping Zhou, Bo Zhao, A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology, ISCA 2009 [6] Jie Chen, Ron C. Chiang, H. Howie Huang, Energy-Aware Writes to Non-Volatile Main Memory ACM SIGOPS Operating Systems Review archive Volume 45 Issue 3, December 2011 [7] Z. Shao, Y. Liu, Y. Chen, and T. Li. Utilizing pcm for energy optimization in embedded systems. In VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, pages 398–403, Aug 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53041 | - |
dc.description.abstract | 中文摘要
電腦架構演變至今,有許許多多的候選者被期待於取代目前的硬盤儲存裝置,在這些候選者當中相變化記憶體是非常備受期待的次世代儲存裝置,由於他有著高密度和極低的使用延遲所以非常適合作為現代架構下的儲存裝置。但是相變化記憶體的高耗能是一個非常嚴重的致命傷,而目前的寫回策略中並大多都是以減少頁缺失次數為目標,並沒有以最佳化儲存系統耗能為出發,另外相變化記憶體的耗能和他所存的資料特徵有關,因此本文提出一個考量儲存資料特徵並且以減少耗能為目標的寫回策略。 關鍵字: 相變化記憶體,儲存裝置系統, 耗能最小化, 寫回策略, 特徵感知 | zh_TW |
dc.description.abstract | ABSTRACT
Phase change memory (PCM) is a potential candidate on the storage applications due to its nanosecond-level access latency and byte-addressability. In addition, with the help of multiple-level-per- cell (MLC) technology, PCM could provide comparable capacity to flash memory. However, adopting MLC PCM needs much larger power consumption than SLC PCM. Thus, in this paper, we exploit a SLC/MLC hybrid memory architecture with the proposed pattern-aware write back policy to minimize the energy consumption on the storage devices In addition, we also propose a counter buffer design to reduce the cost on manipulating data structures, and meanwhile, we design a data migration mechanism to migrate data to MLC PCM when the space of SLC PCM is exhausted. We conducted the experiments on the well-known benchmarks and for which the results are encourage. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T16:40:48Z (GMT). No. of bitstreams: 1 ntu-104-R02922101-1.pdf: 1196747 bytes, checksum: acc4d7061f24a34be443e6274eaff732 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | Contents
Abstract in Chinese i Abstract ii Contents iii List of Figures v List of Tables and Algorithm vi 1 Introduction 1 2 Background and Motivation 3 2.1 Background. . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Content-Based Write Back Policy for Hybrid SLC/MLCPCM Storage Devices 6 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Page State Counter and Counter Buffer Design . . . . . . . . . 8 3.3 Pattern-aware Write Back Policy. . . . . . . . . . . . . . . . . . . . 10 3.4 Storage Data Migration. . . . . . . . . . . . . . . . . . . . . . . 13 4. Experiment 16 4.1 Performance Metrics and Experiment Setup. .. . . . . . . . . 16 4.2 Experiment Results. . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 Performance Evaluation . . . . . . . . . . . . . . . 18 4.2.2 Configuration Considerations. . . . . . . . . . . . . . . . . . . . 20 5. Conclusion 21 Bibliography 22 | |
dc.language.iso | en | |
dc.title | 基於混合式相變化儲存裝置之特徵感知寫入策略 | zh_TW |
dc.title | A Pattern-Aware Write Strategy for Hybrid PCM Storage Devices | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 張原豪 | |
dc.contributor.oralexamcommittee | 楊佳玲,黃柏鈞,王成淵 | |
dc.subject.keyword | 相變化記憶體儲,存裝置系統,耗能最小化,寫回策略,特徵感知, | zh_TW |
dc.subject.keyword | Phase change memory,Storage Device,Minimize energy consumption,Write back Policy,Pattern-aware, | en |
dc.relation.page | 22 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-11 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-104-1.pdf 目前未授權公開取用 | 1.17 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。