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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53032完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Chen-Ming Chen | en |
| dc.contributor.author | 陳成銘 | zh_TW |
| dc.date.accessioned | 2021-06-15T16:40:18Z | - |
| dc.date.available | 2020-08-25 | |
| dc.date.copyright | 2015-08-25 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-11 | |
| dc.identifier.citation | [1] T. Ito and T. Itakura, “A 3-gs/s 5-bit 36-mw flash adc in 65-nm CMOS,” in Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian. IEEE, 2010, pp. 1–4. [2] S.-W. M. Chen and R. W. Brodersen, ”A 6-bit 600-MS/s 5.3-mW asynchronous ADC in0.13-µm CMOS,” IEEE J. Solid-State Circuits, vol.46, no.12, pp. 2669-2680, Dec.2006 [3] J. K. Fiorenza et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS technologies”, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006. [4] L. Brooks and H. Lee, “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC” IEEE J. Solid-State Circuits, vol. 44, no.12, pp. 3329–3343, Dec. 2009. [5] D-L. Shen, Y-M. Tsai, “A 6-bit Bias-less Pipelined ADC with Open-loop Amplifiers”, 20th European Conference on Circuit Theory and Design (ECCTD), 2011, pp.869-872 [6] D-L. Shen, T.-Ch. Lee, “A 6-bit 800-MS/s Pipelined A/D Converter with Open-Loop Ampliers”, IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 258-268, Feb. 2007. [7] C-J. Tseng, C-F. Lai and H-S. Chen, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 61, no. 10,pp. 2805-2815, Oct. 2014 [8] E. Iroaga and B. Murmann, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling” IEEE J. Solid-State Circuits, vol. 42, no.4, pp. 748–756, Ap. 2007. [9] H. San, R. Sugawara, M. Hotta, T. Matssuura and K. Aihara, “An Area-efficient 12-bit 1.25MS/s Radix-value Self-estimated Non-binary ADC with Relaxed Requirements on Analog Components” IEEE Custom Integr. Circuits Conf. Sep. 2014 [10] D-Y. Chang, J. Li and U-K. Moon, “Radix-Based Digital Calibration Techniques for Multi-Stage Recycling Pipelined ADCs,” IEEE Trans. Circuits Syst. I, vol. 51, pp. 2133-2140, Nov. 2004 [11] Nejaati, “Pipeline Analog-to-Digital Converters with radix <2” International Conference on Microelectronics, pp. 39-42, Oct. 31- Nov. 2, 2000 [12] D. W. Cline and P. R. Gray, “A power optimized 13-bit 5Msample/s pipelined analog to digital converter in 1.2 m CMOS,” in Proc. Custom Integrated Circuits Conf., May 1995, pp. 219–222. [13] N. Sasidhar, Y. J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu, and U. K. Moon, “An 1.8V 36-mW 11-bit 80 MS/s Pipelined ADC using capacitor and opamp sharing,” in IEEE Asia Solid-State Circuits Conf., Nov. 2007, pp. 240-243 [14] S. K. Shin, Jacques C. Rudell, Denis C. Daly, Carlos E. Muñoz, D. Y. Chang, Kush Gulati, H. S. Lee, and Matthew Z. Straayer, ” A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1366-1381, Jun. 2014 [15] D.-Y. Chang, “Design technique for a pipelined ADC without using a front-end sample- and-hold amplifier,” IEEE Trans. Circuits Syst. I, vol. 51, pp. 2123–2132, Nov. 2004. [16] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators”, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992 [17] T. Sundström, C. Svensson, “A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1575–1584, Jul. 2011. [18] S. Hashemi and B. Razavi, “A 7.1 mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2013 [19] P. Wu, V. Cheung, and H. C. Luong, “A 1-V 100 MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture,” in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 136–137. [20] B. Razavi, Principles of Data Converter System Design. Wiley-IEEE press, 1995. [21] Timmy Sundstrom, Christer Svensson, and Atila Alvandpour,” A 2.4GS/s, single-channel, 31.3 dB SNDR at Nyquist, Pipelined ADC in 65nm CMOS” IEEE J. Solid-State Circuits, vol. 46, no.7, pp.1575-1584, July 2011. [22] T. Yamase, H. Uchida, and H. Noguchi, “A 22-mW 7 b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture,” in Proc. Symp. VLSI Circuits Dig., Jun. 2011, pp. 124–125. [23] T. Danjo, et al., “A 6-bit, 1-GS/s, 9.9-mW, interpolated subranging ADC in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 673-682, Mar. 2014. [24] D. W. Cline and P. R. Gray, “A power optimized 13-b, 5- Msamplels pipeline analog-to-digital converter in 1pm CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 294-303, Mar. 1996. [25] T. B. Cho and P. R. Gray, “A 10 b, 20 Msamplels pipeline A/D converter,” IEEE J. Solid-state Circuits, vol. 30, pp. 166-172, Mar. 1995 [26] A. M. Ab0 and P. R. Gray, “A 1.5-V, 10-bit, 14.3- MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-state Circuits, vol. 34, pp. 599-606, May 1999 [27] D. Y. Chang, Un-Ku Moon, “Radix-based digital calibration technique for multi-stage ADC”, IEEE ISCAS, pp.796-799, May 2002 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53032 | - |
| dc.description.abstract | 本論文使用不完全趨穩態的技巧，並提出了背景基值偵測來實現一個六位元、每秒二十五億次取樣的導管式類比數位轉換器。不完全趨穩的技巧伴隨著背景基值偵測電路能夠偵測內部真實閉迴路增益，以達到降低類比數位轉換器中運算放大器對於增益和頻寬的需求從而降低運算放大器的功率消耗。 本晶片使用台積電 40nm CMOS一般製程製作。根據模擬結果，在2.5 GS/s 的轉換率下，當輸入頻率為1.25 GHz時，SNDR和SFDR分別為34.3 dB和44.6 dB。在1 V的電壓和1 GS/s的轉換率下的功率消耗為100 mW。全部的晶片面積大小為0.7 mm2，然而主動電路所占的面積只有0.12 mm2。 | zh_TW |
| dc.description.abstract | This thesis adopts incomplete-settling technique with proposed background radix detector to realize 6-bit, 2.5GS/s single channel sub-radix pipelined ADC. A background radix detector is proposed to detect stage gain so that low-gain and low-bandwidth opamp can be utilized to conserve power consumption of opamp. This prototype ADC is fabricated in TSMC 40nm CMOS general-process. According to post-layout simulation results, this prototype ADC SNDR and SFDR are 34.3dB and 44.6dB at 2.5GS/s with 1.25GHz input frequency. The power consumption is 100mW at 1 V supply voltage and 2.5GS/s sampling rate. Active area is 0.12 mm2, and whole chip with pads occupies 0.7 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T16:40:18Z (GMT). No. of bitstreams: 1 ntu-104-R01943115-1.pdf: 6206181 bytes, checksum: d9a7b4bd0d7edd7603fd7dca6d3a7839 (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | CONTENTS 致謝 I 中文摘要 II ABSTRACT III CONTENTS IV LIST OF FIGURES VI LIST OF TABLE IX A 34db SNDR, 2.5GS/s, Sub-Radix Pipeline ADC Using Incomplete Settling Technique with Background Radix Detector 1 Chapter 1 Introduction 1 1.1 High speed Analog-to-Digital Converters 1 1.2 High speed pipeline ADC Using Incomplete Settling 2 1.3 Background Sampling Point Calibration Algorithm 4 1.4 Radix-Based Calibration Technique 7 1.5 Thesis Organization 8 Chapter 2 Proposed Sub-Radix ADC with Background Radix Detector 10 2.1 Incomplete Settling 10 2.2 Sub-Radix 12 2.3 Radix Detect Algorithm 16 2.4 Error Source Analysis 19 2.5 Discussion 30 Chapter 3 Architecture and Circuit Implementation 31 3.1 Proposed Passive Dual S/H Capacitor Array with Early Decision 32 3.2 Pipelined Stage 36 3.3 Radix Detector 43 3.4 Timing arrangement and clock generator 51 Chapter 4 Simulation and Measurement Result 56 4.1 Simulation 56 4.2 Measurement 59 4.3 Summary 67 Chapter 5 Conclusions 68 Reference 69 | |
| dc.language.iso | en | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | Analog to Digital Converter | en |
| dc.title | 一個每秒25億次轉換使用不完全趨穩技巧高速導管式類比數位轉換器伴隨基數偵測 | zh_TW |
| dc.title | A 2.5GS/s, Sub-Radix Pipeline ADC Using Incomplete Settling Technique with Background Radix Detector | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 類比數位轉換器, | zh_TW |
| dc.subject.keyword | Analog to Digital Converter, | en |
| dc.relation.page | 71 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2015-08-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-104-1.pdf 未授權公開取用 | 6.06 MB | Adobe PDF |
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