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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Pei-Keng Tsai | en |
dc.contributor.author | 蔡沛耕 | zh_TW |
dc.date.accessioned | 2021-06-15T13:46:38Z | - |
dc.date.available | 2020-11-27 | |
dc.date.copyright | 2015-11-27 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-11-25 | |
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Park, 'A CMOS programmable gain amplifier with constant current-density based transconductance control,' in 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Oct. 2010, pp. 1-4. [29] H. Elwan, A. Tekin, and K. Pedrotti, 'A differential-ramp based 65 dB-linear VGA technique in 65 nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2503-2514, Sep. 2009. [30] C.-C. Hsu and J.-T. Wu, 'A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier,' IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1663-1670, Oct. 2003. [31] P.-I. Mak, S.-P. U, and R. P. Martins, 'On the design of a programmable-gain amplifier with built-in compact DC-offset cancellers for very low-voltage WLAN systems,' IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 55, no. 2, pp. 496-509, Mar. 2008. [32] C.-C. Hsu and J.-T. Wu, 'A 125 MHz-86 dB IM3 programmable-gain amplifier,' in 2002 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2002, pp. 32-35. [33] P.-I. Mak, S.-P. U, and R. P. Martins, 'A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS,' in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference Sep. 2005, pp. 649-652. [34] S.-C. Tsou, C.-F. Li, and P.-C. Huang, 'A low-power CMOS linear-in-decibel variable gain amplifier with programmable bandwidth and stable group delay,' IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 53, no. 12, pp. 1436-1440, Dec. 2006. [35] F. Xiangning, S. Yutao, and F. Yangyang, 'A CMOS DC offset cancellation (DOC) circuit for PGA of low IF wireless receivers,' in 2010 International Symposium on Signals, Systems and Electronics (ISSSE), Sep. 2010, pp. 1-4. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51728 | - |
dc.description.abstract | 本論文針對可程式化增益放大器(Programmable Gain Amplifier, PGA)提出了幾種增益控制機制。在超音波影像接收器中,需要一個精確的分貝線性PGA,將反射訊號的動態範圍,轉換至類比轉數位轉換器可接受的範圍。為了在很小的增益誤差下,得到較寬的增益範圍與精確的解析度,新提出的PGA採用了指數與近似指數函數兩種變化模式。本論文中討論且分析了幾種可變增益放大器的架構,以及近似指數函數。為了比較兩個不同架構,PGA以0.18-μm互補式金屬氧化物半導體製程製作,包含開路與閉路兩種架構。開路的PGA可以得到較佳的雜訊特性,而閉路的PGA則可以提供較佳的線性度效能。 | zh_TW |
dc.description.abstract | Several gain control mechanisms for the design of programmable gain amplifier (PGA) are presented in this thesis. In ultrasound imaging receivers, an accurate decibel (dB)-linear PGA is required to convert the dynamic range of reflected signal into an acceptable range for the analog-to-digital converter (ADC). In order to obtain a wide dB-linear gain range and fine step resolution with small gain error, both exponential and exponential approximation functions are used in the proposed PGAs. Several variable gain amplifier architectures and exponential approximation functions are discussed and analyzed in this thesis. Two different PGA architectures are fabricated in 0.18-μm CMOS process for comparison, including an open-loop based and a closed-loop based architectures. The open-loop based PGA can achieve a low noise characteristic, while the closed-loop based PGA can provide a better linearity performance. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T13:46:38Z (GMT). No. of bitstreams: 1 ntu-104-R01943164-1.pdf: 6259089 bytes, checksum: 2b5ec1a38d341a545c79f8c2a837af78 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 口試委員審定書 i
致謝 v 摘要 vii Abstract ix Contents xi List of Figures xiii List of Tables xvii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Background of Programmable Gain Amplifier 5 2.1 Linearity 5 2.2 Noise 7 2.2.1 Thermal noise 8 2.2.2 Flicker noise 9 2.3 dB-linear Functions 10 2.4 Fundamentals of Variable Gain Amplifier 17 Chapter 3 Open-Loop Based Programmable Gain Amplifier 21 3.1 Introduction 21 3.2 Circuit Implementation of the Proposed Open-Loop Based Programmable Gain Amplifier 22 3.3 Experimental Results 40 3.4 Conclusion 44 Chapter 4 Closed-Loop Based Programmable Gain Amplifier 45 4.1 Introduction 45 4.2 Circuit Implementation of the Proposed Closed-Loop Based Programmable Gain Amplifier 46 4.3 Experimental Results 60 4.4 Conclusion 65 Chapter 5 Conclusion 67 References 71 | |
dc.language.iso | en | |
dc.title | 混合增益控制機制之CMOS可程式化增益放大器 | zh_TW |
dc.title | CMOS Programmable Gain Amplifier with Hybrid Gain Control Mechanisms | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎,郭建男 | |
dc.subject.keyword | CMOS,可程式化增益放大器,可變增益放大器,分貝線性, | zh_TW |
dc.subject.keyword | CMOS,programmable gain amplifier,variable gain amplifier,decibel linear, | en |
dc.relation.page | 75 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-11-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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ntu-104-1.pdf 目前未授權公開取用 | 6.11 MB | Adobe PDF |
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