請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51105完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Chin-Yu Lin | en |
| dc.contributor.author | 林晉宇 | zh_TW |
| dc.date.accessioned | 2021-06-15T13:25:17Z | - |
| dc.date.available | 2026-05-24 | |
| dc.date.copyright | 2016-06-11 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-05-24 | |
| dc.identifier.citation | [1] H. K. Hong, H. W. Kang, B. Sung, C. H. Lee, M. Choi, H. J. Park, and S. T. Ryu, “An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 470-471.
[2] H. K. Hong, W. Kim, S. J. Park, M. Choi, H. J. Park, and S.T. Ryu, “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2012, pp. 1-4. [3] S. S. Wong, U-F. Chio, Y. Zhu, S. W. Sin, S. P. U, and R. P. Martins, “A 2.3mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC,” IEEE J. of Solid-State Circuits, vol. 48, no. 8, pp. 1-12, Aug. 2013. [4] W. Liu, P. Huang, and Y. Chiu, “A 12-bit 50MS/s 3.3-mW SAR ADC with background digital calibration,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2012, pp. 1-4. [5] W. C. Black and D. A. Hodges, “Time-interleaved converter arrays,” IEEE J. of Solid-State Circuits, vol. 15, no. 12, pp. 1022-1029, Dec. 1980. [6] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, New York, 1995. [7] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997. [8] F. Maloberti, Data Converters, Springer, Dordrecht, 2007. [9] W. Kester, The Data Converter Handbook, Analog Device, Mar. 2004.[Online] Available:www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html [10] F. Goodenough, 'Analog technology of all varieties dominate ISSCC,' Electronic Design, pp. 96, Feb. 1996. [11] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communi -cations, Kluwer Academic Publisher, Boston, 2000. [12] L. Kull et al., “A 32 mW 8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32 nm digital SOI CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2013, pp. 260–261. [13] W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2009, pp. 82–83. [14] C.-Y. Chen, J. Wu, J.-J. Hung, T. Li, W. Liu, and W.-T. Shih, “A 12-bit 3 GS/s pipeline ADC with 0.4 mm2 and 500 mW in 40 nm digital CMOS,” IEEE J. of Solid-State Circuits, vol. 47, no. 4, pp. 1013-1021, Apr. 2012. [15] N. Dolev, M. Kramer, and B. Murmann, “A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using pulsed bucket brigade front-end,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2013, pp. 98-99. [16] A. M. A. Ali et al., “A 14b 1 GS/s RF sampling pipelined ADC with background calibration,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 482-483. [17] P. Harpe, E. Cantatore, and A. van Roermund, “A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step,” IEEE J. of Solid-State Circuits, vol. 48, no.12, pp. 3011-3018, Dec. 2013. [18] J.-H. Tsai et al., “A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS with digital error correction and correlated-reversed switching,” IEEE J. of Solid-State Circuits, vol. 50, no.6, pp. 1382-1398, June 2015. [19] C.-C. Liu, C.-S. Kuo, and Y.-Z. Lin, “A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20 nm CMOS,” IEEE J. of Solid-State Circuits, vol. 20, no.11, pp. 2645-2654, Nov. 2015. [20] M. Furuta, M. Nozawa, and T. Itakura, “A 10-bit, 40-MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle conversion technique,” IEEE J. of Solid-State Circuits, vol. 46, no.6, pp. 1360-1370, Dec. 2011. [21] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR ,” IEEE J. of Solid-State Circuits, vol. 45, no.12, pp. 2647-2654, Dec. 2010. [22] C. C. Lee and M. P. Flynn “A SAR-assisted two-stage pipeline ADC,” IEEE J. of Solid-State Circuits, vol. 46, no.4, pp. 859-869, Apr. 2011. [23] Y.-D. Jeon et al., “A 9.15 mW 0.22mm2 10b 204 MS/s pipelined SAR ADC in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2010, pp. 1-4. [24] Y. Zhu et al., “A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 90-91. [25] F. van der Goes et al., “A 1.5 mW 68 dB SNDR 80 MS/s 2× interleaved SAR-assisted pipelined ADC in 28 nm CMOS,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2014, pp. 200-201. [26] Y. Zhou, B. Xu, and Y. Chiu, “A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector,” IEEE J. of Solid-State Circuits, vol. 50, no.4, pp. 920-931, April 2015. [27] B. Verbruggen, K. Deguchi, B. Malki, and J. Craninckx, “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28 nm digital CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 242-243. [28] Y. Lim and M. P. Flynn “A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2015, pp. 1-3. [29] R. Wang, U.-F. Chio, S.-W. Sin, S.-P. U, Z.-H. Wang, and R. P. Martins, “A 12-bit 110-MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique,” in Proc. IEEE ESSCIRC, 2012, pp. 265-268. [30] C.-Y. Lin and T.-C. Lee, “A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 244-245. [31] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion technique－Part I,” IEEE J. of Solid-State Circuits, vol. SC-10, no.6, pp. 371-379, Dec. 1975. [32] M. Inerfield et al., “An 11.5-ENOB 100-MS/s 8mW Dual-Reference SAR ADC in 28nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 246-247. [33] M. Ding et al., “A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2015, pp. 1-3. [34] W.-H. Tseng et al., “A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2015, pp. 1-4. [35] C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.-C. Huang, Y.-H. Lin, C.-C. Lee, and B. Razavi, “An 11b 800MS/s time-Interleaved ADC with digital background calibration,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2007, pp. 464-465. [36] S. K. Gupta, M. A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE J. of Solid- State Circuits, vol. 41, no. 12, pp. 2650-2657, Dec. 2006. [37] T. C. Choi and R. W. Brodersen, “Consideration for high-frequency switched-capacitor ladder filters,” IEEE Trans. Circuits Syst, vol. CAS-27, pp. 545-552, Jun. 1980. [38] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS,” IEEE J. of Solid-State Circuits, vol. 36, no.12, pp. 1847-1858, Dec. 2002. [39] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. of Solid-State Circuits, vol. 45, no.4, pp. 731-740, Apr. 2010. [40] B.-N. Fang and J.-T. Wu, “A 10-bit 300-MS/s pipelined ADC with digital calibration and digital bias generation,” IEEE J. of Solid- State Circuits, vol. 48, no. 3, pp. 670-683, Mar. 2013. [41] K. Ragab, L. Chen, A. Sanyal, and N. Sun, “Digital background calibration for pipelined ADCs based on comparator decision time quantization,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 62, no. 5, pp. 456-460, May 2015. [42] K. Nagaraj et al., “A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,” IEEE J. of Solid- State Circuits, vol. 32, no. 3, pp. 312-320, Mar. 1997. [43] B. Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between frequency response and settling time of operational amplifier,” IEEE J. of Solid- State Circuits, vol. SC-9, no. 6, pp. 347-352, Dec. 1974. [44] V. Tripathi and B. Murmann, “A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2014, pp. 1-4. [45] S. Lee, A. P. Chandrakasan, and H. S. Lee, “A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 384–385. [46] B.-R.-S. Sung et al., “A 21fJ/conv-step 9 ENOB 1.6GS/s 2x time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 464–465. [47] B. Razavi, “Design considerations for interleaved ADCs,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug. 2013. [48] D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE J. Solid State Circuits, vol.48, no. 4, pp. 971–982, Apr. 2013. [49] N. Le Dortz et al., “A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp.386–388. [50] I. Ahmed, J. Mulder, and D. A. Johns, “A low-power capacitive charge pump base pipelined ADC,” IEEE J. Solid State Circuits, vol.45, no. 5, pp. 1016–1027, May 2010. [51] J. W. Nam, D. Chiong, and M. S. W. Chen, “A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2013, pp. 1-4. [52] H.-K. Hong et al., “A 2.6b/cycle-architecure-based 10b 1.7GS/s 15.4mW 4x-time-interleaved SAR ADC with a multistep hardware-retirement technique,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp.470–471. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51105 | - |
| dc.description.abstract | 類比數位轉換器在現今的SoC系統中扮演關鍵的元件，因為其連接了真實世界的類比訊號與數位信號處理器。隨著近年來攜帶式裝置迅速發展，高速低功耗的類比數位轉換器需求也隨之劇增。此篇論文提出了兩種類比數位轉換器之設計，達到高速、低功率消耗等設計目標。
本論文中首先提出一個雙通道十二位元、兩億一千萬赫茲取樣率的管線式連續漸進暫存類比數位轉換器。轉換器架構上分為三級，前兩級使用了提出的被動式餘值轉移的技巧來節省功耗，後兩級則採用主動式放大來實現。提出的架構實現於六十五奈米製程中，在1伏特供應電壓下消耗5.3毫瓦。當輸入低頻信號與操作於奈奎斯頻率時，信噪失真比(SNDR)分別為63.5分貝與60.1分貝。 第二部份則是包含了應用於下一代行動通訊射頻前端系統中一個十位元、二十六億赫茲取樣率時間交錯式連續漸進暫存類比數位轉換器。論文中實現了十六通道十位元、二十六億赫茲取樣率時間交錯式連續漸進暫存類比數位轉換器，並採用差值取樣輔助型類比數位轉換器與數位混波校正技術。提出的類比數位轉換器實現於四十奈米製程中，在1.1伏特供應電壓下消耗18.4毫瓦。當操作於奈奎斯頻率時，信噪失真比(SNDR)為50.6分貝。 | zh_TW |
| dc.description.abstract | Analog-to-digital converter (ADC) has been recognized as one of the crucial building blocks in the modern SoC system because it provides the link between the real-world analog information and the digital signal processors (DSPs). The demand on high-speed and low-power ADCs has increased as many portable applications grow rapidly in recent years. In this dissertation, two ADCs are presented to achieve high-speed and low-power design.
The first part of this dissertation demonstrates a 12-b, 210-MS/s 2-channel interleaved pipelined-SAR ADC. The proposed ADC is partitioned into 3 stages with passive residue transfer technique between the 1st and the 2nd stages for power saving and active residue amplification between the 2nd and the 3rd stages. The prototype, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at DC and 60.1 dB near Nyquist-rate. The second part present a 10-b, 2.6-GS/s time-interleaved SAR ADC for the RF front-end of the next-generation mobile system. A 16-channel time-interleaved 10-b SAR ADC, employing the proposed delta-sampling auxiliary SAR ADC and digital mixing calibration to correct timing skew error, achieves a 2.6-GS/s sampling rate. The ADC has been fabricated in a 40-nm CMOS technology and achieves a 50.6-dB SNDR at Nyquist rate while dissipating 18.4 mW from a 1.1-V power supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T13:25:17Z (GMT). No. of bitstreams: 1 ntu-105-D98943015-1.pdf: 3422266 bytes, checksum: 80913430001262d53ec495d47b990ab9 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 iiii Abstract iv Contents v List of Figures ixx List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converters 5 2.1 Introduction 5 2.2 ADC Performance Metrics 5 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 5 2.2.2 Signal-to-Noise Ratio (SNR) 8 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 9 2.2.4 Effective Number of Bits (ENOB) 10 2.2.5 Spurious-Free Dynamic Range (SFDR) 10 2.2.6 Figure of Merit (FoM) 11 2.3 Architectures of Analog-to-Digital Converters 11 2.3.1 Flash ADC 11 2.3.2 Sub-Ranging ADCs 12 2.3.3 Successive Approximation Register ADC 14 2.3.4 Pipelined ADC 15 2.3.5 Time-Interleaved ADC 16 2.4 Error Sources in Time-Interleaved ADCs 17 2.4.1 Offset Mismatch 18 2.4.2 Gain Mismatch 19 2.4.3 Phase Skew 20 Chapter 3 A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC 23 3.1 Introduction 23 3.2 Prior Pipelined-SAR ADCs 25 3.3 Proposed Passive Residue Transfer Technique 30 3.4 Proposed Architecture 35 3.4.1 Design Considerations of the Proposed ADC 37 3.4.2 Embedded 2.8-bit SAR Conversion 39 3.5 Circuit Implementation 43 3.5.1 Backend Stages Design 43 3.5.2 Foreground DAC Gain Calibration 45 3.5.3 Residue Amplifier 48 3.6 Experimental Results 51 3.7 Summary 56 Chapter 4 A 10-bit 2.6-GS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration 57 4.1 Introduction 57 4.2 Timing Skew Calibration 58 4.3 Prior Arts 60 4.4 Proposed Timing Skew Calibration 64 4.4.1 Digital Mixing Method 64 4.4.2 Proposed Digital Timing Skew Correction 66 4.4.3 Frequency-Domain Analysis of the Timing Skew Calibration 73 4.4.4 Design Consideration 80 4.4.5 Signal Difference Extraction 82 4.5 Delta-Sampling SAR ADC 83 4.5.1 Delta-Sampling Operation 83 4.5.2 Delta-Sampling SAR ADC 85 4.6 Interleaved Architecture 89 4.7 Mismatches between Main and Auxiliary ADCs 91 4.8 Experimental Results 94 4.9 Summary 98 Chapter 5 Conclusions and Future Works 99 5.1 Conclusions 99 5.2 Recommendations for Future Investigation 99 Bibliography 101 Publication List 109 | |
| dc.language.iso | en | |
| dc.subject | 時間偏斜校正 | zh_TW |
| dc.subject | 多通道類比數位轉換器 | zh_TW |
| dc.subject | 時間偏斜校正 | zh_TW |
| dc.subject | 管線式連續漸進暫存類比數位轉換器 | zh_TW |
| dc.subject | 多通道類比數位轉換器 | zh_TW |
| dc.subject | 管線式連續漸進暫存類比數位轉換器 | zh_TW |
| dc.subject | timing skew calibration | en |
| dc.subject | Pipelined-SAR ADC | en |
| dc.subject | Time-Interleaved ADC | en |
| dc.subject | timing skew calibration | en |
| dc.subject | Pipelined-SAR ADC | en |
| dc.subject | Time-Interleaved ADC | en |
| dc.title | 高速與低功耗之類比數位轉換器設計 | zh_TW |
| dc.title | Design of High-Speed and Low-Power Analog-to-Digital Converters | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 吳介琮(Jieh-Tsorng Wu),郭泰豪(Tai-Haur Kuo),謝志成(Chih-Cheng Hsieh),劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 管線式連續漸進暫存類比數位轉換器,多通道類比數位轉換器,時間偏斜校正, | zh_TW |
| dc.subject.keyword | Pipelined-SAR ADC,Time-Interleaved ADC,timing skew calibration, | en |
| dc.relation.page | 110 | |
| dc.identifier.doi | 10.6342/NTU201600259 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-05-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-105-1.pdf 未授權公開取用 | 3.34 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。