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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Yi-An Hsu | en |
| dc.contributor.author | 許毅安 | zh_TW |
| dc.date.accessioned | 2021-06-15T12:55:24Z | - |
| dc.date.available | 2021-07-26 | |
| dc.date.copyright | 2016-07-26 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-07-17 | |
| dc.identifier.citation | [1] K. Yoon, G. Kim, W. Lee, T. Song, J. Lee, H. Lee, K. Park, and J. Kim, “Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer,” in Proc. IEEE Electron. Packag. Technol. Conf., Singapore, Dec. 2009, pp. 702-706.
[2] J. Cho, and J. Kim, “TSV modeling and noise coupling in 3D IC,” in Proc. IEEE Electron. System-Integration Technol., Berlin, Germany, Sep. 2010, pp. 1-6. [3] J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, “Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package,” in Proc. IEEE Electron. Compon. and Technol., Las Vegas, NV, Jun. 2010, pp. 667-672. [4] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, “High-frequency scalable modeling and analysis of a differential signal through-silicon via,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 181-195, Feb. 2011. [5] Z. Chen, Q. Wang, J. Xie, J. Tian, J. Jiang, Y. Li, and W. Yin, “Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling,” in Proc. IEEE Circuits and Syst., Beijing, China, May 2013, pp. 2646-2649. [6] J. Cho, E. Song, K. Yoon, J. S. Pak, J. Kim, W. Lee, T. Song, K. Kim, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, “Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 220–233, Feb. 2011. [7] S. Uemura, Y. Hiraoka, T. Kai, and S. Dosho, “Isolation techniques against substrate noise coupling utilizing through silicon via (TSV) for RF/mixed-signal SoCs,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 810–810, Apr. 2012. [8] C.-D. Wang, Y.-J. Chang, Y.-C. Lu, P.-S. Chen, W.-C. Lo, Y.-P. Chiou, and T.-L. Wu, “ABF-based TSV arrays with improved signal integrity on 3-D IC/interposers: equivalent models and experiments,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 3, no. 10, pp. 1744-1753, Oct. 2013. [9] C.-H. Cheng, T.-Y. Cheng, C.-H. Du, Y.-C. Lu, Y.-P. Chiou, Sally Liu, T.-L. Wu, “An equation-based circuit model and its generation tool for 3-D IC power delivery networks with an emphasis on coupling effect,” IEEE Trans. Compon. Packag. Manuf. Technol., vol.4, no.6, pp. 1062-1070, June. 2014. [10] T.-Y. Cheng, C.-D. Wang, Y.-P. Chiou, and T.-L Wu, “Accuracy-improved through-silicon-via model using conformal mapping technique,” in Proc. IEEE. Elect. Performance Electron. Package. Systems, San Jose, CA, Oct. 2011, pp. 189-192. [11] T.-Y. Cheng, C.-D. Wang, Y.-P. Chiou, and T.-L Wu, “A new model for through-silicon vias on 3-D IC using conformal mapping method,” IEEE Microw. Compon. Lett., vol. 22, no. 6, pp. 303–305, Jun. 2012. [12] Y. Zhou, H. Chen, X. Wang, W. Mao, W. Shi, and Y. Chang, “Modeling differential Through-Silicon-Vias (TSVs) with large signal, non-linear capacitance,” in Proc. IEEE. Elect. Performance Electron. Package. Systems, Tempe, AZ, Oct. 2012, pp. 276-279. [13] J. Cho, J. Kim, J. S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Nonlinear effects of TSV and harmonic generation,” in Proc. IEEE Electron. Compon. Technol., San Diego, CA, Jun. 2012, pp. 834-838. [14] N. Azuma, Y. Kanda, and M. Nagata, “Extraction of lumped RC elements representing substrate coupling of RF devices,” in Proc. IEEE Radio- Freq. Integr. Technol., Beijing, China, Dec. 2011, pp. 217-220. [15] X. Gu, J. A. Silberman, A. M. Young, K. A. Jenkins, B. Dang, Y. Liu, X. Duan, R. Gordin, S. Shlafman, and D. Goren, “Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 3, no. 11, pp. 1917–1925, Nov. 2013. [16] Y. Araga, M. Nagata, G. V. der Plas, P. Marchal, M. Libois, A. La Manna, W. Zhang, G. Beyer, and E. Beyne “Measurements and analysis of substrate noise coupling in TSV-based 3-D integrated circuits,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 4, no. 6, pp. 1026–1037, Jun. 2014. [17] J. Cho, J. Shim, E. Song, J. S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Active circuit to through silicon via (TSV) noise coupling,” in Proc. IEEE. Elect. Performance Electron. Package. Systems, Portland, OR, Oct. 2009, pp. 97-100. [18] B. Goplen, and S. Sapatnekar, “Through silicon via (TSV) noise coupling effects on RF LC-VCO in 3D IC,” in Proc. IEEE. Elect. Performance Electron. Package. Systems, Portland, OR, Oct. 2014, pp. 53-56 [19] B. D. Gaynor, and S. Hassoun, “Simulation methodology and evaluation of through silicon via (TSV)FinFET noise coupling in 3-D integrated circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 8, pp. 1499-1507, Jul. 2015. [20] N. H. Khan, S. M. Alam, and S. Hassoun, “Through-silicon via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs,” in Proc. IEEE 3D System Integr., San Francisco, CA, Sep. 2009, pp. 1–7. [21] B. Van Zeghbroeck, Principles of Electronic Devices, New Jersey: Prentice Hall, 2011. [22] C. R. Paul, Analysis of Multiconductor Transmission Lines, New York: Wiley, 1994. [23] Li Lu, “A Study of Through-Silicon Via (TSV) Induced Transistor Variation,” M.S. thesis, Massachusetts Institute of Technology, MA, 2011. [24] S. Ryu, K. Lu, T. Jiang, J. Im, R. Huang, and P. S. Ho, “Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration,” IEEE Trans. Device Mater. Rel., vol. 12, no. 2, pp. 255-262, Jun. 2012. [25] B. Goplen, and S. Sapatnekar, “Placement of thermal vias in 3- D ICs using various thermal objectives,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 692-709, Apr. 2006. [26] B. Xie, M. Swaminathan, K. J. Han, and J. Xie, “Coupling analysis of through-silicon via (TSV) arrays in silicon interposers for 3D systems,” in Proc. IEEE Int. Symp. Electromagn. Compat., Long Beach, CA, Aug. 2011, pp. 16-21. [27] S. Seth, D. H. Kwon, S. Venugopalan, S. W. Son, Y. Zuo, V. Bhagavatula, J. Lim, D. Oh, and T. B. Cho, “A dynamically biased multiband 2G/3G/4G cellular transmitter in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 5, pp. 1096-1108, May 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/50736 | - |
| dc.description.abstract | 本論文主要分析三維積體電路中，由於矽穿孔上電流產生的基板雜訊對電路造成的影響。透過參考三維傳輸線矩陣方法，本文提出一準確之等效電路模型，可以在極近的矽穿孔間距之下，得到準確的基板雜訊模擬結果。在提出的等效電路模型中，考慮了矽基板的半導體效應，以及用八角型等效電路模擬圓柱型的矽穿孔。為驗證提出之預測方法，本文利用ANSYS HFSS以及TCAD Sentaurus等模擬軟體分別進行頻域以及時域的驗證。本論文亦利用所提出的等效電路模型，進行基板上之熱生成預測，以及和主動電路進行共模擬，得到主動電路受基板雜訊的影響。 | zh_TW |
| dc.description.abstract | In this research, the influence of the substrate noise induced by the through silicon via in 3-D ICs is analyzed. An equivalent circuit model is proposed based on the 3-D transmission line matrix (3-D TLM) method. The proposed equivalent circuit model is able to predict the substrate noise accurately under extremely small P/D ratio of the TSVs, and the semiconductor effect is considered. To verify the proposed model, ANSYS HFSS and TCAD Sentaurus are used in frequency and time domain simulation. The proposed model can also be used in the heat generation prediction on the silicon substrate and the co-simulation with the active circuit. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T12:55:24Z (GMT). No. of bitstreams: 1 ntu-105-R02942141-1.pdf: 3793751 bytes, checksum: 0d5108d08f17b1cca44b4019330dfa3a (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 中文摘要 v
ABSTRACT vii CONTENTS ix LIST OF FIGURES xi LIST OF TABLES xv ACRONYMS xvii Chapter 1 Introduction 1 1.1 Research Motivation 1 1.2 Literature Review 2 1.3 Contribution 4 1.4 Thesis Organization 5 Chapter 2 TSV Based 3-D ICs Equivalent Circuit Modeling 7 2.1 Silicon Substrate Modeling 8 2.2 Doping Profile Modeling 11 2.3 TSV Modeling 13 2.3.1 Metal Core Resistance Modeling 16 2.3.2 Multi-TSV Inductance Modeling 16 2.3.3 Depletion Region Modeling 18 2.4 Model Verification 23 2.4.1 Frequency-Domain Analysis 24 2.4.2 Time-Domain Analysis 27 Chapter 3 Co-Simulation with Active Circuit 35 3.1 Simulation Scenario 36 3.2 Signal Waveform 38 3.2.1 Noise on the Substrate 38 3.2.2 Influence on Signal of the CMOS inverter 39 3.3 Output Noise Analysis 43 3.4 Keep-Out Zone Analysis 47 3.4.1 Definition of Keep-Out Zone 47 3.4.2 Depletion Region Influence 49 3.4.3 Substrate Noise Mitigation Designs 50 Chapter 4 Heat Generation of Substrate in 3-D ICs 59 4.1 Heat Generation Distribution in Substrate 60 4.2 Heat Generation Verification 64 4.3 Simulation Results and Discussion 66 4.3.1 Influence of TSV Arrangement 68 4.3.2 Influence of Oxide Thickness 70 Chapter 5 Conclusions 71 5.1 Conclusions 71 5.2 Suggestions for Future Works 72 REFERENCES 73 PUBLICATION LIST 77 | |
| dc.language.iso | en | |
| dc.subject | 基板熱生成 | zh_TW |
| dc.subject | 基板雜訊 | zh_TW |
| dc.subject | 矽穿孔 | zh_TW |
| dc.subject | 三維傳輸線矩陣 | zh_TW |
| dc.subject | 等效電路模型 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 矽穿孔 | zh_TW |
| dc.subject | 基板雜訊 | zh_TW |
| dc.subject | 基板熱生成 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 等效電路模型 | zh_TW |
| dc.subject | 三維傳輸線矩陣 | zh_TW |
| dc.subject | equivalent circuit model | en |
| dc.subject | 3-D IC | en |
| dc.subject | through silicon via (TSV) | en |
| dc.subject | substrate noise | en |
| dc.subject | heat production on substrate | en |
| dc.subject | 3-D transmission line matrix (3-D TLM) method | en |
| dc.title | 三維積體電路中基於三維傳輸線模型之基板雜訊以及基板熱生成之預測方法 | zh_TW |
| dc.title | An Accurate Prediction Method of Substrate Noise and Thermal Issue in 3-D ICs Based on Modified 3-D TLM | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳瑞北,盧奕璋,盧信嘉 | |
| dc.subject.keyword | 三維積體電路,矽穿孔,基板雜訊,基板熱生成,三維傳輸線矩陣,等效電路模型, | zh_TW |
| dc.subject.keyword | 3-D IC,through silicon via (TSV),substrate noise,heat production on substrate,3-D transmission line matrix (3-D TLM) method,equivalent circuit model, | en |
| dc.relation.page | 77 | |
| dc.identifier.doi | 10.6342/NTU201600933 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-07-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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