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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Yi-Hsun Chang | en |
| dc.contributor.author | 張藝薰 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:46:47Z | - |
| dc.date.available | 2019-10-14 | |
| dc.date.copyright | 2016-10-14 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-12 | |
| dc.identifier.citation | [1] Bob Verbrug et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS, ” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 252–253, Feb. 2008.
[2] Bob Verbrug et al., “ A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 2080–2090, Dec. 2010. [3] Zhiheng Cao, Shouli Yan, and Yunchu Li, “A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 0.13um CMOS,” Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 542–543, Feb., 2008 [4] Chi-Hang Chan et al., 'A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure,' in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 86- 87. [5] Hung-Yen Tai et al., “A 0.004mm2 Single-Channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS,” in IEEE Asian Solid-State Circuits Conf., 2013, pp. 277–280. [6] Stephane Le Tual et al, “A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 382–383, Feb., 2014 [7] Jie Fang et al., “A 5GS/s 10b 76mW Time-interleaved SAR ADC in 28nm CMOS,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4, 2015. [8] Shuo-Wei Michael Chen and Robert W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006. [9] Tao Jiang et al, “A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive approximation ADC with improved feedback delay in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444–2453, Oct. 2012. [10] Lukas Kull et al, “A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049–3058, Dec. 2013. [11] Chun-Cheng Liu, et al, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [12] Peter Schvan et al., “A 24GS/s 6b ADC in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp.544-545, 2008 [13] Yuriy M Greshishchev et al., “A 40GS/s 6b ADC in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp.390-391, 2010 [14] Manar El-Chammas and Boris Murmann, “A 12 GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011. [15] Chun-Cheng Huang, Chung-Yi Wang, and Jieh-Tsorng Wu, “A CMOS 6-bit 16-GS/s time-interleaved ADC using digital background calibration techniques,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 848–858, Apr. 2011. [16] Aida Varzaghani et al., “A 10.3-GS/s, 6-bit flash ADC for 10G Ethernet applications,” IEEE J. Solid-State Circuits, vol. 48, no.12, pp. 3038–3048, Dec. 2013. [17] Yida Duan and Elad Alon, “A 12.8 GS/s time-interleaved ADC with 25 GHz effective resolution bandwidth and 4.6 ENOB,” IEEE J. Solid-State Circuits, vol. 49, no.8, pp. 1725–1738, Aug. 2014. [18] Behzad Razavi, “Principle of data conversion system design,” Wiley-IEEE Press, New York, 1995 [19] N. Kurosawa et al., “Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems, ” IEEE Trans. Circuits Syst.Ⅰ, Fundam. Theory Appl., vol.48, no.3, pp.261–271, Mar. 2001. [20] Pieter J. A. Harpe et al., “A 0.47–1.6 mW 5-bit 0.5–1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1594–1602, Jul. 2012. [21] Mikael Gustavsson, J. Jacob Wikner, and Nianxiong Nick Tan, “CMOS Data Converters for Communications,” Kluwer Academic Publisher, Boston, 2000. [22] Sandeep K.. Gupta, Michael A. Inerfield, and Jingbo Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2650–2657, Dec. 2006. [23] Kostas Doris et al., “A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2821–2833, Dec. 2011. [24] Nicolas Le Dortz et al., “A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2014, pp. 386‒388. [25] Cheng-Chung Hsu et al., “An 11b 800MS/s time-interleaved ADC with digital background calibration,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 464–465. [26] Dusan Stepanovic and Borivoje Nikolic, “A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 971–982, Apr. 2013. [27] Lukas Kull et al., “A 35mW8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS, ” Symposium on VLSI Circuits Digest of Technical Papers, pp. C260 – C261, 2013. [28] I-Ning Ku et al., “A 40-mW 7-bit 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communications,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1854–1865, Aug. 2012. [29] Lin Wu et al., “A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2001, pp. 396–397. [30] Chan-Hong Park et al., “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 777–783, May. 2001. [31] Hsiang-Hui Chang et al., “A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1051–1061, May. 2006. [32] Keng-Jan Hsiao and Tai-Cheng Lee, “An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2478–2487, Sept. 2009. [33] Huawen Jin and d Edward K. F. Lee, “A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC’s,” IEEE Transaction on Circuits And Systems—II: Analog And Digital Signal Processing, vol. 47, no. 7, Jul. 2000 [34] E. Iroaga et al., “A Background Correction Technique for Timing Errors in Time-Interleaved Analog-to-Digital Converters,” IEEE International Symposium on Circuits and Systems, vol. 6, pp. 5557 – 5560, 2005. [35] S. M. J et al., “A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter With Digital Background Calibration, ” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618–1627, Dec. 2002. [36] Shafiq M. Jamal et al., “Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter,” IEEE Transactions on Circuits And Systems – I: Regular Papers, vol. 51, no. 1, Jan. 2004. [37] Vijay Divi and Gregory W. Wornell, “Blind Calibration of Timing Skew in Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of Selected Topics in Signal Processing, vol. 3, no. 3, pp. 509–522, Jun. 2009. [38] Richard L. Burden et al., “Numerical Analysis: Prindle, Webber & Schmit,” 1981, pp. 88–92. [39] David Camarero et al., “Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs,” IEEE Transactions on Circuits And Systems – I: Regular Papers, vol. 55, no. 11, Dec. 2008. [40] Hegong Wei et al., “An 8 Bit 4 GS/s 120 mWCMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, Aug. 2014. [41] Sunghyuk Lee et al., “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration,” IEEE Journal of Solid-State Circuits, vol. 49, no. 12, Dec. 2014. [42] Vanessa H.-C. Chen and Lawrence Pileggi, “A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI,” IEEE Journal of Solid-State Circuits, vol. 49, no. 12, Dec. 2014. [43] Tzu-Yi Tang, Tsung-Heng Tsai and Kevin Chen et al., “Timing mismatch background calibration for time-interleaved ADCs,” in TENCON 2012 - 2012 IEEE Region 10 Conference, Nov. 2012, pp. 1–4. [44] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999. [45] Yan Zhu; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U; Martins, R.P.; Maloberti, F., 'A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,' IEEE Journal of Solid-State Circuits, vol.45, no.6, pp.1111,1121, June 2010 [46] Chien-Hung Kuo; Cheng-En Hsieh, 'A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,' ESSCIRC (ESSCIRC), 2011 Proceedings of the , vol., no., pp.475,478, 12-16 Sept. 2011 [47] Wicht, B.; Nirschl, T.; Schmitt-Landsiedel, D., 'Yield and speed optimization of a latch-type voltage sense amplifier,' Solid-State Circuits, IEEE Journal of, vol.39, no.7, pp.1148, 1158, July 2004 [48] Shan Jiang et al., “An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit,” IEEE Transactions On Circuits And Systems—I: Regular Papers, vol. 55, no. 6, Jul. 2008. [49] Franz Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13µm CMOS,” IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2002, pp. 136–137. [50] Hung-Yen Tai et al., “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 92–93, 2012 [51] Xiang Gao et al., “Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers,” IEEE International Symposium on Circuits and Systems (ISCAS), 2007. [52] Xiang Gao et al., “Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation,” IEEE Transactions on Circuits and Systems—II, vol. 55, no. 3, Mar. 2008 [53] Sung-Hyun YANG et al., “A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free ,” IEICE Trans. Electron., vol.e86-C, no.3 Mar. 2003 [54] Neil H. E. Weste and David Money Harris, “integrated circuit design 4th.” [55] Ba-Ro-Saim Sung et al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in Proc. IEEE Asian Solid-State Circuits Conf., 2013, pp. 281–284. [56] Hokyu Lee et al., “A 6-bit 2.5-GS/s time-interleaved analog-to-digital converter using resistor-array sharing digital-to-analog converter,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 2371–2383, Nov. 2015. [57] Chi-Hang Chan et al., “A 5.5mW 6b 5GS/s 4x-Interleaved 3b/cycle SAR ADC in 65nm CMOS,” Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp.466–467, Feb. 2015. [58] Chip Implementation Center (CIC), “PCB Fabrication Design Rule Manual (DRM),” http://www2.cic.org.tw/~cis/PCB/doc/DRM_PCB.pdf | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49763 | - |
| dc.description.abstract | 由於無線通訊系統的演進，對於高速取樣頻率以及中高解析度的類比數位轉換器的需求日漸增加。
本論文提出一個六位元每秒四十五億次取樣的時間交錯式之連續漸進暫存式的類比數位轉換器，以一個40奈米一般製程的CMOS製程實現。此架構由16個子通道之連續漸進暫存式的類比數位轉換器組成，以一個源極隨耦器作緩衝去推動4個通道類比數位轉換器為一組，共分成4組的方式，達到有效隔絕通道間的重疊以及高頻寬之效果。透過零交越（zero crossing）的偵測技巧，達成通道間的時間偏移補償。另一方面，在子通道之電容陣列作任意加權分佈（AWCA）可以去除比較器在轉換過程的動態偏移誤差。 實驗結果顯示在每秒四十億次的轉換下，DNL和INL分別為+0.17/-0.29 LSB和+0.20/-0.18 LSB。在每秒四十五億的轉換及輸入頻率為一億赫茲，SNDR以及SFDR分別為32.15 dB、41.04 dB。在1.2V的供應電壓下，功率消耗為 24.9 mW（不含I/O pad）。最後，品質因數（FoM）為159 fJ/c.-s.， 核心面積佔 0.195 平方毫米，全部面積大小為1.275平方毫米。 | zh_TW |
| dc.description.abstract | As the advance of wireless communication system, the requirements for ADC with high speed sampling rate and medium resolution gradually increase.
A 6-bit 4.5GS/s time-interleaved SAR ADC is presented in 40nm General process (GP) of CMOS technology in this thesis. The architecture consists of 16 SAR ADCs and is divided into 4 groups. Each group has 4 sub-ADC driven by a source follower as buffer to achieve isolation from overlapping channel and high bandwidth. In addition, the skew detection using zero crossing technique can compensate time skew error from channel mismatch without extra reference source. On the other hand, any-weighted-capacitor-array (AWCA)can suppress dynamic offset owing to the conversion process of comparator in sub-ADC. The measurement results show that the linearity of DNL and INL are -0.17/-0.29 LSB and +0.2/-0.18 LSB, respectively at 4-GS/s with input frequency of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB respectively operated at 4.5GS/s with input frequency of 1 GHz. The power consumes 24.9 mW at 1.2V. Finally, the FoM is 159 fJ/c.-s. The active area occupies 0.195 mm2, and the overall chip occupies 1.275 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:46:47Z (GMT). No. of bitstreams: 1 ntu-105-R02943023-1.pdf: 3417073 bytes, checksum: 9c2c7dda61c0d4ab8bf840e768f95806 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III List of Figures VIII List of Tables XVI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Analog to Digital Converter 4 2.1 Introduction 4 2.2 Performance Metrics 4 2.2.1 Static Performance 4 2.2.2 Dynamic Performance 6 2.3 ADC Architectures 9 2.3.1 Flash Architecture 9 2.3.2 Pipelined Architecture 11 2.3.3 Successive-Approximation-Register Architecture 12 2.3.4 Time-Interleaved Architecture 14 2.4 Error Source in Time-Interleaved ADC Architecture 16 2.4.1 Offset Mismatch 16 2.4.2 Gain Mismatch 19 2.4.3 Timing Skew Mismatch 22 Chapter 3 Time-Interleaved SAR ADC 26 3.1 Introduction 26 3.2 Front-end sampling Architecture 27 3.2.1 Multiple Rank 27 3.2.1.1 Prior Work 30 3.2.2 One Rank 33 3.2.2.1 Prior Work 35 3.3 Calibration 38 3.3.1 Offset Calibration 40 3.3.1.1 All Analog Domain 40 3.3.1.2 All Digital Domain 41 3.3.1.3 Mixed Domain 43 3.3.2 Gain Calibration 44 3.3.3 Timing Calibration 45 3.3.3.1 All Analog Domain 45 3.3.3.2 All Digital Domain 46 3.3.3.2.1 Reference-Based Technique 47 3.3.3.2.2 Filter-Based Technique 49 3.3.3.3 Mixed Domain 53 3.3.3.3.1 Variance with Redundancy 54 3.3.3.3.2 Sampling Edge Estimation 56 3.3.3.3.3 Zero-Crossing 57 3.3.3.3.4 Correlation 60 Chapter 4 Proposed Architecture and Calibration 63 4.1 Front-end Architecture 63 4.2 Calibration 66 4.2.1 Offset and Gain 66 4.2.2 Timing Skew 66 4.2.2.1 Detection Algorithm 67 4.2.2.2 Consideration of Skew Adjustment 71 Chapter 5 Circuit Implementation 75 5.1 Introduction 75 5.2 The Building Blocks of Time-Interleaved SAR ADC 75 5.2.1 Front-End Architecture 76 5.2.1.1 Sampling Switch 76 5.2.1.2 Source Follower 82 5.2.1.3 Bias Circuit of Source Follower 89 5.2.2 Single Channel SAR ADC 90 5.2.2.1 Capacitor Array 93 5.2.2.2 Comparator 99 5.2.2.3 SAR Logic 102 5.2.3 Clock Generator 106 5.2.3.1 Architecture 107 5.2.3.2 TSPC D Flip Flop 112 5.2.3.3 Timing Adjustment Circuit 118 5.2.4 Post-Stage Circuit 123 5.2.4.1 Digital Signal Output Circuit 123 5.2.4.2 Frequency Divider 124 5.2.4.3 Decoder 125 5.3 Overall ADC Simulation Results 128 Chapter 6 Measurement 133 6.1 Introduction 133 6.2 Floor Plan and Layout Design 133 6.3 PCB Design 137 6.4 Test Setup 139 6.5 Measurement Results 143 6.6 Discussion 151 6.6.1 Differential Input with Different RF Transformers 151 6.6.2 Insufficient Skew Tuning Range 156 6.7 Summary 159 Chapter 7 Conclusions and Future Work 161 7.1 Conclusions 161 7.2 Future Work 162 Bibliography 164 | |
| dc.language.iso | en | |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 時間偏移校正 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | 時間不匹配 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 時間交錯式 | zh_TW |
| dc.subject | analog to digital converter | en |
| dc.subject | time skew calibration | en |
| dc.subject | timing mismatch | en |
| dc.subject | low power | en |
| dc.subject | high speed | en |
| dc.subject | SAR | en |
| dc.subject | time-interleaved | en |
| dc.title | 一個有時間偏移校正之多通道連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | A Multi-Channel SAR ADC with timing mismatach calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡宗亨,陳怡然,劉深淵 | |
| dc.subject.keyword | 類比至數位轉換器,時間交錯式,連續漸進式,高速,低功率,時間不匹配,時間偏移校正, | zh_TW |
| dc.subject.keyword | analog to digital converter,time-interleaved,SAR,high speed,low power,timing mismatch,time skew calibration, | en |
| dc.relation.page | 172 | |
| dc.identifier.doi | 10.6342/NTU201601744 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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