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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林浩雄(Hao-Hsiung Lin) | |
dc.contributor.author | Chen-Lun Ting | en |
dc.contributor.author | 丁振倫 | zh_TW |
dc.date.accessioned | 2021-06-15T11:42:37Z | - |
dc.date.available | 2018-08-24 | |
dc.date.copyright | 2016-08-24 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-15 | |
dc.identifier.citation | [1] https://ourworldindata.org/technological-progress/
[2] Mike Mayberry, “Enabling Breakthroughs in Technology,” p.15, 2011, http://download.intel.com/newsroom/kits/research/2011/pdfs/Components-Research_Enabling_Breakthroughs_Technology.pdf [3] Ravi Pillarisetty, “Academic and industry research progress in germanium nanodevices”, Nature, 479, pp.324-p.328, 2011. [4] Z. Tang, Z. Liu, and X. Zhu, “Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories”, Trans. Electr. Electron. Mater., 11, No. 4, pp. 155-165, 2010. [5] S. Z. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 2006. [6] Roman Engel-Herbert, Yoontae Hwang, and Susanne Stemmer, “Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces”, J. Appl. Phys., 108, 124101, 2010. [7] L. M. Terman, Solid-State Electron., 5, p. 284, 1962. [8] R. Castagne, A. Vapaille,”Description of the SiO2-Si interface Properties by Means of Very Low Frequency MOS Capacitance Measurements”, Surf. Sci, 28, pp. 157-193, 1971. [9] E. H. Nicollian, A. Goetzberger, “The Si-SiO2 Interface-Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique,” Bell Syst. Tech. J., 46, pp. 1055-1133, 1967. [10] Koen Martens et al., “On the Correct Extraction of Interface Trap Density of MOS Devices with High-Mobility Semiconductor Substrates”, IEEE Trans. Electron Dev., 55, No. 2, 2008. [11] T. Suntola, 'Atomic Layer Epitaxy', MATER SCI REP, 4, 1989. [12] Sentaurus Device User Guide, Version G-2012.06. [13] Erik Lind, Yann-Michel Niquet, Hector Mera, and Lars-Erik Wernersson, “Accumulation capacitance of narrow band gap metal-oxide-semiconductor capacitors”, Appl. Phys. Lett., 96, 233507, 2010. [14] http://www.ioffe.ru/SVA/NSM/Semicond/InAs/bandstr.html [15] T. P. O’Regan, P. K. Hurley, B. Sorée, and M. V. Fischetti, “Modeling the capacitance-voltage response of In0.53Ga0.47As metal-oxide-semiconductor structures: Charge quantization and nonparabolic corrections”, Appl. Phys. Lett., 96, 213514, 2010. [16] Guy Brammertz et al., “A Combined Interface and Border Trap Model for High-Mobility Substrate Metal-Oxide-Semiconductor Devices Applied to In0.53Ga0.47As and InP Capacitors”, IEEE Trans. Electron Dev., 58, No. 11, 2011. [17] J. Robertson, Y. Guo, and L. Lin, “Defect state passivation at III-V oxide interfaces for complementary metal–oxide–semiconductor devices”, J. Appl. Phys., 117, 112806, 2015. [18] G. Brammertz, H. -C. Lin, M. Caymax, M. Meuris, M. Heyns, and M. Passlack, “On the interface state density at In0.53Ga0.47As /oxide interfaces”, Appl. Phys. Lett., 95, 202109, 2009. [19] H. D. Trinh et al., “Electrical Characterization of Al2O3/n-InAs Metal-Oxide-Semiconductor Capacitors with Various Surface Treatments”, IEEE Electron Dev Lett., 32, No. 6, 2011. [20] Jun Wu (2016), Vertical III-V/High-k Nanowire MOS Capacitors and Transistors (Doctoral dissertation), Department of Electrical and Information Technology, Lund University. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49697 | - |
dc.description.abstract | 本論文探討由三五族材料半導體(III-V semiconductor)以及高介電係數材料(high-κ material)所構成之金氧半電容元件(Metal-Oxide-Semiconductor capacitor, MOSCAP)特性,三五族材料選擇為砷化銦(InAs),此材料因其有效電子質量很小,其電子遷移率很大,然而此亦導致砷化銦之傳導帶能帶密度(Density of state, DOS)較小,此項特性使得其元件特性和以矽為基板之金氧半電容元件有很大的差異。因此,本論文使用半導體元件模擬工具(Technology Computer Aided Design, TCAD),以數值模擬的方式,對由砷化銦以及高介電係數材料所構成之理想金氧半電容元件特性作探討。
此外,三五族和高介電係數材料之介面品質為影響其元件特性的關鍵,因此如何得到較為正確的介面缺陷密度(interface trap density, Dit)是ㄧ項重要的議題。傳統用於分析矽及二氧化矽介面之方法,包括電導法和電容法,在分析三五族及高介電係數材料介面時,受其材料特性所致,會受到ㄧ些限制。因此,本研究以前述之TCAD模擬理想金氧半電容元件電容-電壓曲線為基礎,再進一步考慮介面缺陷密度,以和實驗量測所得的低頻(1kHz)電容-電壓曲線擬合的方式,估計其介面缺陷密度之大小和分布。 | zh_TW |
dc.description.abstract | In the thesis, the characteristics of the Metal-Oxide-Semiconductor capacitor (MOSCAP), fabricated by III-V semiconductors and high-κ materials, are investigated. The III-V semiconductor we choose is InAs. Because of its small electron effective mass, InAs is allowed to have high electron mobility. However, the property also comes with the small conduction band density of state (DOS). It gives rise to the difference in the device performances, compared with Si-based MOSCAP. Therefore, we use Technology Computer Aided Design (TCAD) to investigate the properties of the ideal MOSCAPs, fabricated by III-V semiconductors and high-κ materials.
Additionally, the quality of high-κ material/III-V semiconductor interface is essential because it causes critical effects on the device’s performances. Consequently, how to extract the correct interface trap density (Dit) is crucial. The orthodox approaches to extract interface trap density in Si/SiO2 interface, including the conductance method and the capacitance method, encounter some limitations. As a result, the ideal capacitance-voltage data simulated by TCAD, is fitted with our experimental low frequency capacitance-voltage data, by considering the effect of interface trap density. Through the specific method, we can get the information of interface trap density thoroughly. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T11:42:37Z (GMT). No. of bitstreams: 1 ntu-105-R03943111-1.pdf: 2316873 bytes, checksum: 7e657be75d2f18d7119eeb7706d68291 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 中文摘要 I
Abstract II 目錄 III 圖目錄 VI 表目錄 IX 第一章 緒論 1 1.1 前言 1 1.2 研究動機 3 1.2.1 通道材料選擇 3 1.2.2 介電材料選擇 4 1.2.3 高介電係數之氧化物與三五族半導體材料介面特性 5 1.3 論文架構 6 第二章 理論基礎與實驗儀器 6 2.1 理想金氧半電容元件之物理特性 7 2.1.1 累積區(accumulation region) 10 2.1.2 空乏區(depletion region) 11 2.1.3 反轉區(inversion region) 13 2.1.4 平帶情況 15 2.2 氧化層之缺陷電荷 16 2.2.1 介面缺陷電荷(interface trap charge, Qit) 17 2.2.2 固定氧化層電荷(fixed Oxide charge, Qf) 17 2.2.3 氧化層缺陷電荷(oxide trap charge, Qot) 17 2.2.4 移動離子電荷(mobile ion charge, Qm) 18 2.3 氧化層之缺陷電荷 19 2.3.1 高頻電容法 19 2.3.2 低頻電容法 21 2.3.3 高-低頻電容法 21 2.3.4 電導法 22 2.4 原子層沉積系統 25 2.5 TCAD軟體 27 第三章 理想之金氧半電容元件模擬 28 3.1 TCAD模擬流程 28 3.2 網格密度之決定 29 3.2.1 元件架構 29 3.2.2 不同網格密度之比較 30 3.2.3 數值解與理論計算之比較 32 3.3 理想之金氧半電容元件模擬 33 3.3.1 元件架構及參數 33 3.3.2 費米-狄拉克分布(Fermi-Dirac Distribution) 34 3.3.3 非拋物線性傳導帶能帶結構 41 3.3.4 完整之傳導帶能帶結構 44 第四章 非理想金氧半電容元件之擬合 47 4.1 實驗流程及結果 47 4.2 考慮非理想效應之擬合 49 4.2.1 介面缺陷之種類 49 4.2.2 介面缺陷之影響 50 4.2.3 擬合流程 51 4.2.4 擬合結果與討論 52 第五章 結論 55 參考文獻 56 | |
dc.language.iso | zh-TW | |
dc.title | 以TCAD模擬n型砷化銦及高介電係數氧化層之金氧半電容元件特性 | zh_TW |
dc.title | TCAD Simulation of n-type InAs MOSCAPs with High-κ Dielectric Layer | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 葉凌彥,林佑儒,陳書涵 | |
dc.subject.keyword | 砷化銦,金氧半電容元件,半導體元件模擬工具,電容-電壓模擬,介面缺陷密度, | zh_TW |
dc.subject.keyword | InAs,metal-oxide-semiconductor,TCAD,capacitance-voltage simulation,interface trap density, | en |
dc.relation.page | 58 | |
dc.identifier.doi | 10.6342/NTU201602561 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-08-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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