以TCAD模擬n型砷化銦及高介電係數氧化層之金氧半電容元件特性

Abstract

本論文探討由三五族材料半導體(III-V semiconductor)以及高介電係數材料(high-κ material)所構成之金氧半電容元件(Metal-Oxide-Semiconductor capacitor, MOSCAP)特性，三五族材料選擇為砷化銦(InAs)，此材料因其有效電子質量很小，其電子遷移率很大，然而此亦導致砷化銦之傳導帶能帶密度(Density of state, DOS)較小，此項特性使得其元件特性和以矽為基板之金氧半電容元件有很大的差異。因此，本論文使用半導體元件模擬工具(Technology Computer Aided Design, TCAD)，以數值模擬的方式，對由砷化銦以及高介電係數材料所構成之理想金氧半電容元件特性作探討。 此外，三五族和高介電係數材料之介面品質為影響其元件特性的關鍵，因此如何得到較為正確的介面缺陷密度(interface trap density, Dit)是ㄧ項重要的議題。傳統用於分析矽及二氧化矽介面之方法，包括電導法和電容法，在分析三五族及高介電係數材料介面時，受其材料特性所致，會受到ㄧ些限制。因此，本研究以前述之TCAD模擬理想金氧半電容元件電容-電壓曲線為基礎，再進一步考慮介面缺陷密度，以和實驗量測所得的低頻(1kHz)電容-電壓曲線擬合的方式，估計其介面缺陷密度之大小和分布。

In the thesis, the characteristics of the Metal-Oxide-Semiconductor capacitor (MOSCAP), fabricated by III-V semiconductors and high-κ materials, are investigated. The III-V semiconductor we choose is InAs. Because of its small electron effective mass, InAs is allowed to have high electron mobility. However, the property also comes with the small conduction band density of state (DOS). It gives rise to the difference in the device performances, compared with Si-based MOSCAP. Therefore, we use Technology Computer Aided Design (TCAD) to investigate the properties of the ideal MOSCAPs, fabricated by III-V semiconductors and high-κ materials. Additionally, the quality of high-κ material/III-V semiconductor interface is essential because it causes critical effects on the device’s performances. Consequently, how to extract the correct interface trap density (Dit) is crucial. The orthodox approaches to extract interface trap density in Si/SiO2 interface, including the conductance method and the capacitance method, encounter some limitations. As a result, the ideal capacitance-voltage data simulated by TCAD, is fitted with our experimental low frequency capacitance-voltage data, by considering the effect of interface trap density. Through the specific method, we can get the information of interface trap density thoroughly.