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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉(Hsin-Chia Lu) | |
dc.contributor.author | Yun-Hsuan Yeh | en |
dc.contributor.author | 葉鋆宣 | zh_TW |
dc.date.accessioned | 2021-06-15T11:31:29Z | - |
dc.date.available | 2021-08-30 | |
dc.date.copyright | 2016-08-30 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-16 | |
dc.identifier.citation | [1] Chunyuan Zhou, He Qian, and Zhiping Yu, “A lumped elements varactor-loaded transmission-line phase shifter at 60GHz,” in 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 656-658, November 2010.
[2] Pen-Jui Peng, Jui-Chih Kao, and Huei Wang, “A 57-66 GHz vector sum phase shifter with low phase/amplitude error using a wilkinson power divider with LHTL/RHTL elements,” in 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1-4, October 2011. [3] Jen-Chu Wu, Jui-Chih Kao, Jhe-Jia Kuo, Kun-Yao Kao, and Kun-You Lin, “A 60-GHz single-ended-to-differential vector sum phase shifter in CMOS for phased-array receiver,” in 2011 IEEE MTT-S International Microwave Symposium, pp. 1-4, June 2011. [4] Wei-Tsung Li, Yun-Chieh Chiang, Jeng-Han Tsai, Hong-Yuan Yang, Jen-Hao Cheng, and Tian-Wei Huang, “60-GHz 5-bit phase shifter with integrated VGA phase-error compensation,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no.3, pp. 1224-1235, March 2013. [5] Pen-Jui Peng, “Design of phase shifter for microwave and millimeter-wave applications,” Graduate Institute of Communication Engineering Master Thesis, National Taiwan University, June 2010. [6] Byung-Wook Min and Gabriel M. Rebeiz, “Single-ended and differential Ka-band BiCMOS phased array front-ends,” IEEE Journal of Solid-State Circuits, vol. 43, no.10, pp. 2239-2250, October 2008. [7] Hyo-Sung Lee and Byun-Wook Min, “W-band CMOS 4-bit phase shifter for high power and phase compression points,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no.1, pp. 1-5, January 2015. [8] Fanyi Meng, Kaixue Ma, Kiat Seng Yeo, Shanshan Xu, Chirn Chye Boon, and Wei Meng Lim, “Miniaturized 3-bit phase shifter for 60 GHz phased-array in 65 nm CMOS technology,” IEEE Microwave and Wireless Components Letters, vol. 24, no.1, pp. 50-52, January 2014. [9] Christopher R. Valenta and Gregory D. Durgin, “Harvesting wireless power: survey of energy-harvester conversion efficiency in far-field, wireless power transfer systems,” IEEE Microwave Magazine, vol. 15, no.4, pp. 108-120, June 2014. [10] Jun Yi, Wing-Hung Ki, and Chi-Ying Tsui, “Analysis and design strategy of UHF micro-power CMOS rectifiers for micro-sensor and RFID applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no.1, pp. 153-166, January 2007. [11] Joonhyung Lim, Hanjin Cho, Koonshik Cho, and Tahjoon Park, “High sensitive RF-DC rectifier and ultra-low power DC sensing circuit for waking up wireless system,” in 2009 Asia Pacific Microwave Conference, pp. 237-240, December 2009. [12] Hao Gao, Ulf Johannsen, Marion K. Matters-Kammerer, Dusan Milosevic, A. Bart Smolders, Arthur van Roermund, and Peter Baltus, “A 60-GHz rectenna for monolithic wireless sensor tags,” in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), pp. 2796-2799, May 2013. [13] Soumyajit Mandal and Rahul Sarpeshkar, “Low-power CMOS rectifier design for RFID applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no.6, pp. 1177-1188, June 2007. [14] Pascal Burasa, Nicolas G. Constantin, and Ke Wu, “High-efficiency wideband rectifier for single-chip batteryless active millimeter-wave identification (MMID) tag in 65-nm bulk CMOS technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 62, no.4, pp. 1005-1011, April 2014. [15] Y. Wang and M. Sawan, “High-efficiency CMOS rectifier dedicated for multi-band ambient RF energy harvesting,” in 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 179-182, December 2014. [16] Giuseppe Papotto, Francesco Carrara, and Giuseppe Palmisano, “A 90-nm CMOS threshold-compensated RF energy harvester,” IEEE Journal of Solid-State Circuits, vol. 46, no.9, pp. 1985-1997, September 2011. [17] Hyouk-Kyu Cha, Woo-Tae Park, and Minkyu Je, “A CMOS rectifier with a cross-coupled latched comparator for wireless power transfer in biomedical applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no.7, pp. 409-413, July 2012. [18] Kai Kang, Fujiang Lin, Duy-Dong Pham, James Brinkhoff, Chun-Huat Heng, Yong-Xin Guo, and Xiaojun Yuan, “A 60-GHz OOK receiver with an on-chip antenna in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no.9, pp. 1720-1731, September 2010. [19] Erik Ojefors, Ullrich R. Pfeiffer, Alvydas Lisauskas, and Hartmut G. Roskos, “A 0.65 THz focal-plane array in a quarter-micron CMOS process technology,” IEEE Journal of Solid-State Circuits, vol. 44, no.7, pp. 1968-1976, July 2009. [20] Richard Al Hadi, Hani Sherry, Janusz Grzyb, Yan Zhao, Wolfgang Forster, Hans M. Keller, Andreia Cathelin, Andreas Kaiser, and Ullrich R. Pfeiffer, “A 1 k-pixel video camera for 0.7-1.1 Terahertz imaging applications in 65-nm CMOS, ” IEEE Journal of Solid-State Circuits, vol. 47, no.12, pp. 2999-3012, December 2012. [21] Kangyang Xu, Xin Yang, Wei Wang, and Toshihiko Yoshimasu, “44-GHz, 0.5-V compact power detector IC in 65-nm CMOS,” in 2014 IEEE International Wireless Symposium (IWS), pp. 1-3, March 2014. [22] Jae Jin Lee, Dong Yun Jung, Ki Chan Eun, Seong Jun Cho, and Chul Soon Park, “A 60 GHz low power CMOS demodulator for multi-gigabit wireless receiver systems,” in 2007 Asia-Pacific Microwave Conference, pp. 1-4, December 2007. [23] Mei-Chao Yeh, Zuo-Min Tsai, Ren-Chieh Liu, Kun-You Lin, Ying-Tang Chang, and Huei Wang, “Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no.1, pp. 31-39, January 2006. [24] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [25] Thierry Taris, Valerie Vigneras, and Ludivine Fadel, 'A 900MHz RF energy harvesting module,' in 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 445-448, June 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49496 | - |
dc.description.abstract | 本論文主要研究領域為開關式相移器與功率偵測電路,由於高速通訊蓬勃發展,除了傳統的語音傳輸,更進一步發展至圖片與影片之傳輸。因此通信訊號的頻率日益提升,以應付高速通訊之需求。現今以5G通訊系統為通信發展之主流,操作頻率為38 GHz,因此本論文所提之電路即以此頻段作為發展之重點。
本論文前半段則針對各式相移器與功率偵測電路架構進行介紹,並就其原理加以分析,考量使用的用途,選定開關式相移器做為本論文所提之架構。二版之相移器晶片則針對第一版電路由於電晶體模型不準造成之相位誤差部分加以改良,提出一整合開關式相移器與反射式相移器之整合電路,以連續可調之反射式相移器修正因製程影響所造成之相位誤差,使相位誤差可小於 ,振幅誤差則可小於1.5 dB。而於功率偵測電路部分,首先選定之架構為交叉耦合式整流電路,由於此電路架構具有較高之輸出電壓,其輸出電壓範圍為1 mV至700 mV,有利於簡化功率偵測電路之設計,並與天線整合為同一晶片,可以減少電路間轉接損失並降低製作成本。其最低可偵測功率為 dBm,直流功耗為29 mW。而二版之功率偵測電路,則為了提升原先電路之偵測功率範圍,故採用自混式整流電路,並輔以低雜訊放大器與運算放大器,使可偵測之最小功率可達 dBm,輸出電壓範圍為125 mV至1.6 V,直流功耗為31.5 mW,使此功率偵測電路能具有更廣泛的應用度。 而本論文後半段則是分別對於所提之四種電路進行設計,針對其架構進行更進一步的分析,同時並採用ADS軟體進行電路模擬,被動元件之電磁模擬則使用Sonnet軟體。本論文之所提之四個電路分別使用台積電之40 nm、65 nm、90 nm與180 nm CMOS製程實現,而所提之開關式相移器與具有天線之功率偵測電路已於國立台灣大學電機二館進行高頻量測驗證,其量測結果可佐證本論文之模擬結果,並可證實本論文所提之電路架構確實可實現相移器與功率偵測電路。 | zh_TW |
dc.description.abstract | This thesis studies the switch type phase shifters and power detectors. To satisfy the demand of high-speed mobile wireless communications, the 5G mobile communication is under developing and the operating frequency is 38 GHz. Therefore, this thesis chooses this band as the operating frequency of proposed circuits.
This thesis first reviews the architectures of different types of phase shifters and power detectors, and also analyzes the operation principles of these circuits. Considering the application, this thesis chooses switch type phase shifter as main architecture. To reduce the phase error caused by the inaccuracy of transistor model, this thesis proposes a phase shifter combining the switch type and reflection type phase shifter. With continuous tuning voltage, it can correct the phase error caused by process variation. It can achieve the phase imbalance of less than and the amplitude imbalance of less than 1.5 dB. On the other hand, cross-coupled pair rectifier has been chosen for the first architecture of power detector. The circuit has the advantage of high output voltage ranging from 1 mV to 700 mV without additional op-amp, so it can simplify the circuit design. Furthermore, the cross-coupled pair rectifier is integrated with an on-chip antenna. It can not only reduce the transfer loss between rectifier and antenna but also reduce production costs. The minimum detectable power of this circuit is dBm and the DC power consumption is 29 mW. In order to increase the detectable power range, the second version of power detector applies self-mixing rectifier as detector circuit, and adds the low noise amplifier and operation amplifier. It achieves the minimum detectable power at dBm and the output voltage range at 125 mV to 1.6 V. The total DC power consumption is 31.5 mW. In this thesis, the proposed circuits have been designed by Keysight ADS and Sonnet for the circuit and EM simulation. The circuits developed in TSMC 40 nm, 65 nm, 90 nm and 180 nm CMOS technology respectively. The switch type phase shifter and power detector with on-chip antenna have been measured in National Taiwan University E.E. Building No.2 with high frequency measurement instrument. The measurement results prove the properties of proposed circuits. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T11:31:29Z (GMT). No. of bitstreams: 1 ntu-105-R03943028-1.pdf: 5490836 bytes, checksum: 33f33239e54e72153397f7261939aad4 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xi Chapter 1 簡介 1 1.1 研究動機 1 1.2 文獻回顧 4 1.3 各章節介紹重點 6 Chapter 2 相移器與功率偵測電路概論 7 2.1 簡介 7 2.2 相移器電路介紹 7 2.2.1 傳輸線式相移器 7 2.2.2 向量和式相移器 9 2.2.3 開關式相移器 10 2.2.4 反射式相移器 16 2.3 功率偵測電路介紹 18 2.3.1 倍壓式整流器 18 2.3.2 交叉耦合式整流器 20 2.3.3 自混式整流器 22 Chapter 3 相移器電路設計 24 3.1 簡介 24 3.2 設計流程 24 3.3 開關式相移器電路 25 3.3.1 電路架構 25 3.3.2 電晶體尺寸設計 27 3.3.3 電磁模擬 31 3.3.4 模擬結果 33 3.3.5 電路佈局圖與晶片照片 37 3.4 具有校正功能之相移器電路 39 3.4.1 電路架構 39 3.4.2 電晶體尺寸設計 40 3.4.3 電磁模擬 41 3.4.4 模擬結果 42 3.4.5 電路佈局圖 50 3.5 電路特性比較 50 Chapter 4 功率偵測電路設計 52 4.1 簡介 52 4.2 設計流程 53 4.3 具有天線之功率偵測電路晶片 54 4.3.1 電路架構 54 4.3.2 電晶體尺寸設計 56 4.3.3 電磁模擬 60 4.3.4 模擬結果 61 4.3.5 電路佈局圖與照片 63 4.3.6 電路特性比較 66 4.4 自混式功率偵測電路 67 4.4.1 電路架構 67 4.4.2 電晶體尺寸設計 68 4.4.3 電磁模擬 70 4.4.4 模擬結果 71 4.4.5 電路佈局圖 75 4.4.6 電路特性比較 75 Chapter 5 量測 77 5.1 印刷電路板電路設計 77 5.1.1 開關式相移器電路板設計 77 5.1.2 具有天線之功率偵測電路晶片之電路板設計 78 5.2 開關式相移器量測數據 79 5.2.1 反射係數 79 5.2.2 各級相位差與振幅差 80 5.2.3 量測架設與照片 82 5.2.4 電路除錯 84 5.3 具有校正功能之相移器量測數據 87 5.4 功率偵測電路量測數據 88 5.4.1 反射係數 88 5.4.2 輸入功率與輸出電壓轉換曲線 90 5.4.3 量測架設與照片 93 Chapter 6 結論 95 參考文獻 97 | |
dc.language.iso | zh-TW | |
dc.title | 應用於5G通訊之相移器與功率偵測晶片 | zh_TW |
dc.title | Phase Shifters and Power Detectors for 5G Communication | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),林坤佑(Kun-You Lin),蔡政翰(Jeng-Han Tsai) | |
dc.subject.keyword | 5G通訊,開關式相移器,反射式相移器,功率偵測電路,交叉耦合式整流器,自混式整流器, | zh_TW |
dc.subject.keyword | 5G communication,switch type phase shifter,reflection type phase shifter,power detector,cross-coupled pair rectifier,self-mixing rectifier, | en |
dc.relation.page | 100 | |
dc.identifier.doi | 10.6342/NTU201603004 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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