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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 盧信嘉(Hsin-Chia Lu) | |
| dc.contributor.author | Chao-Che Chang | en |
| dc.contributor.author | 張肇哲 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:29:26Z | - |
| dc.date.available | 2025-08-12 | |
| dc.date.copyright | 2020-08-21 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-12 | |
| dc.identifier.citation | [1] Jri Lee, Yi-An Li, Meng-Hsiung Hung, and Shih-Jou Huang, “A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2746 - 2756, Dec. 2010. [2] E. Björnson. (2019). Beamforming from distributed arrays. [Online]. Available: https://ma-mimo.ellintech.se/2019/01/25/beamforming-from-distributed-arrays/ [3] D. M. Pozar, 4th, Ed. Microwave Engineering. John Wiley Sons, 2011. [4] N. Instruments. (2019). Millimeter wave: band battle. [Online]. Available: https://www.ni.com/zh-tw/innovations/white-papers/16/mmwave--the-battle-of-the-bands.html [5] (2020). Taiwan IOT Technology and Industry Association. [Online]. Available: http://www.twiota.org/eventDetails.aspx?id=23dd87b2-5c1a-4c6f-97fb-ba73d6d1844b [6] J. Y.-C. Liu, C.-T. Chan, and S. S. Hsu, 'A K-band power amplifier with adaptive bias in 90-nm CMOS,' in 2014 9th European Microwave Integrated Circuit Conference, Oct. 2014, pp. 432-435. [7] H. Alsuraisry, J.-H. Cheng, S.-J. Luo, W.-J. Lin, J.-H. Tsai, and T.-W. Huang, 'A 24-GHz transformer-based stacked-FET power amplifier in 90-nm CMOS technology,' in 2015 Asia-Pacific Microwave Conference (APMC), Dec. 2015, vol. 3, pp. 1-3. [8] Y.-C. Lee, T.-Y. Chen, and J. Y.-C. Liu, 'An adaptively biased stacked power amplifier without output matching network in 90-nm CMOS,' in 2017 IEEE MTT-S International Microwave Symposium (IMS), June 2017, pp. 1667-1690. [9] J.-L. Lin, Y.-H. Lin, Y.-H. Hsiao, and H. Wang, 'A K-band transformer based power amplifier with 24.4-dBm output power and 28% PAE in 90-nm CMOS technology,' in 2017 IEEE MTT-S International Microwave Symposium (IMS), June 2017, pp. 31-34. [10] C. Yu, J. Feng, and D. Zhao, 'A Ka-band 65-nm CMOS neutralized medium power amplifier for 5G phased-array applications,' in 2018 IEEE MTT-S International Wireless Symposium (IWS), May 2018, pp. 1-3. [11] S. N. Ali, P. Agarwal, J. Baylon, S. Gopal, L. Renaud, and D. Heo, 'A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays,' in 2018 IEEE International Solid-State Circuits Conference-(ISSCC), Feb. 2018, pp. 406-408. [12] S. N. Ali, P. Agarwal, L. Renaud, R. Molavi, S. Mirabbasi, and P. P. Pande, 'A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable gate–drain neutralization for 28-GHz 5G radios,' IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 5, pp. 2231-2245, May 2018. [13] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari, 'A highly efficient and linear power amplifier for 28-GHz 5G phased array radios in 28-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3020-3036, Dec. 2016. [14] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech House, 2006. [15] H. Zhang and Q. Xue, '60-GHz CMOS current-combining PA with adaptive back-off PAE enhancement,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 823-827, Sep. 2016. [16] J.-H. Tsai, H.-Y. Chang, P.-S. Wu, Y.-L. Lee, T.-W. Huang, and H. Wang, 'Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers,' IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 6, pp. 2487-2496, June 2006. [17] Y.-C. Hsu, K.-Y. Kao, J.-C. Kao, T.-C. Tsai, and K.-Y. Lin, 'A 60 GHz CMOS power amplifier with modified pre-distortion linearizer,' in 2013 IEEE MTT-S International Microwave Symposium Digest (IMS), June 2013, pp. 1-4. [18] K.-W. Chen, 'Research on pre-distortion techniques for K-band CMOS power amplifier,' Master Thesis, Graduate Institute of Communication Engineering, National Taiwan University, July 2012. [19] J.-H. Tsai, C.-H. Wu, H.-Y. Yang, and T.-W. Huang, 'A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer,' IEEE Microwave and Wireless Components Letters, vol. 21, no. 12, pp. 676-678, Dec. 2011. [20] T.-C. Tsai, 'Research on adaptive-bias technique for K-band CMOS power amplifier,' Master Thesis, Graduate Institute of Communication Engineering, National Taiwan University, July 2011. [21] H. Zhang and Q. Xue, '60-GHz CMOS current-combining PA with adaptive back-off PAE enhancement,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 823-827, Sep. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49454 | - |
| dc.description.abstract | 本篇論文提出了兩個使用台積電90-nm互補式金氧半導體製程於Ka頻段之功率放大器，設計目標是提升電路的線性度、輸出功率、功率附加效率及退縮6-dB處功率附加效率。 於第一個電路中，主要採用了雙重中和技術，功率放大器是使用2.4 V偏壓供電。此差動疊接架構是由四個單級疊接架構與變壓器組合而成，功率放大器在2.4 V以及偏壓0.7 V的情況下，實際量測可得Ka頻段操作小訊號增益14 dB、OP1dB為19.56 dBm以及飽和輸出功率20.24 dBm，於OP1dB點的PAE與PAE的最大值分別為21.45 %與21.9 %，而在P1dB退縮6 dB點的PAE為10.14 %。 第二個電路，主要是以第一顆架構為基礎，並加入線性器及自動調整偏壓等技術來達到提升功率附加效率。此功率放大器在2.4 V以及偏壓0.8 V的情況下，實際量測可得Ka頻段操作小訊號增益14.68 dB、OP1dB為20.15 dBm以及飽和輸出功率20.71 dBm，於OP1dB點的PAE與PAE的最大值分別為25.77 %與25.99%，而在P1dB退縮6 dB點的PAE為15.73 %。與第一顆晶片相比，在相近增益及OP1dB之下，對應之PAE都有明顯的改善。 | zh_TW |
| dc.description.abstract | In this thesis, two Ka-band power amplifier chips implemented in TSMC 90-nm CMOS process are proposed to improve the linearity, output power, PAE and back-off 6-dB efficiency. For the first chip, a Ka-band power amplifier using 2.4 V supply voltage utilizing double neutralization technique is designed and measured. The differential cascode architecture combines four single-stage cascode cells and transformers. With 2.4 V supply voltage and 0.7 V bias voltage, the measured small signal gain is 14 dB, OP1dB is 19.56 dBm, and saturation power is 20.24 dBm. The PAE at OP1dB and peak are 21.45 % and 21.9% respectively. The PAE at 6-dB back-off from P1dB is 10.14 %. The second chip is based on the first one by adding linearizer and adaptive-bias to improve back-off power-added-efficiency. With 2.4 V supply voltage and 0.8 V bias voltage, the measured small signal gain is 14.68 dB, OP1dB is 20.15 dBm, and saturation power is 20.71 dBm. The PAE at OP1dB and peak are 25.77 % and 25.99 % respectively. The PAE at 6-dB back-off from P1dB is 15.73 %. Compared with the first chip, the second chip has similar gain and OP1dB, but PAE at different power levels are all improved. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:29:26Z (GMT). No. of bitstreams: 1 U0001-1208202014315100.pdf: 8483916 bytes, checksum: c6faad31b15ff620b84ad86812294de2 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 # 誌謝 i 摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xi Chapter 1 簡介 1 1.1 研究動機與背景 1 1.2 頻段選取 3 1.3 文獻回顧 4 1.4 論文貢獻 6 1.5 各章節介紹重點 7 Chapter 2 功率放大器概論 8 2.1 基礎介紹 8 2.2 功率放大器之重要參數 9 2.2.1 小訊號放大器理論[3] 9 2.2.2 負載線與負載拉移理論[14] 11 2.2.3 功率 14 2.2.4 效率 15 2.2.5 線性度 16 2.3 電晶體疊接技術 20 2.4 預失真線性器 22 2.4.1 線性器基本介紹 22 2.4.2 線性器操作原理[16] 24 2.4.3 已發表文獻：採用90°延遲線線性器之功率放大器[17] [18] 26 2.4.4 已發表文獻：基極偏壓改動線性器之功率放大器[19] 27 2.5 自動調整偏壓技術 28 2.5.1 自動調整偏壓操作概念 29 2.5.2 自動調整偏壓操作原理[20] 30 2.5.3 已發表文獻：採用自動調整偏壓之電流合成功率放大器[21] 30 2.5.4 已發表文獻：自動調整偏壓之不須匹配堆疊式功率放大器[8] 32 Chapter 3 採用雙重中和技術之功率放大器 34 3.1 功率放大器設計 34 3.1.1 設計流程 35 3.1.2 電晶體尺寸挑選 36 3.1.3 差動疊接架構功率放大器 39 3.1.4 中和技術 40 3.1.5 功率合成 43 3.1.6 匹配 44 3.1.7 電磁模擬 45 3.1.8 結果 50 3.2 模擬結果 50 3.2.1 小訊號模擬 51 3.2.2 穩定度 51 3.2.3 大訊號模擬 53 3.2.4 三階互調失真模擬 53 3.2.5 特性比較 55 Chapter 4 具自動調整偏壓及線性化技術且使用雙重中和技術功率放大器 56 4.1 功率放大器設計 56 4.1.1 自動調整偏壓電路設計流程 57 4.1.2 自動調整偏壓電路 58 4.1.3 自動調整偏壓電路之各項參數調整及說明 59 4.1.4 線性器設計 60 4.1.5 結果 65 4.2 模擬結果 65 4.2.1 小訊號模擬 66 4.2.2 穩定度 67 4.2.3 自動調整偏壓模擬情形 69 4.2.4 大訊號模擬 70 4.2.5 三階互調失真模擬 71 4.2.6 特性比較 73 Chapter 5 量測 74 5.1 量測環境 74 5.2 採用雙重中和技術之功率放大器 76 5.2.1 小訊號量測 77 5.2.2 大訊號量測 79 5.2.3 三階互調失真量測 82 5.3 具自動調整偏壓及線性化技術且使用雙重中和技術功率放大器 83 5.3.1 小訊號量測 85 5.3.2 大訊號量測 87 5.3.3 三階互調失真量測 90 5.4 小結 91 Chapter 6 結論 96 參考文獻 97 | |
| dc.language.iso | zh-TW | |
| dc.subject | 中和技術 | zh_TW |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | 線性度 | zh_TW |
| dc.subject | Ka頻段 | zh_TW |
| dc.subject | 5G | zh_TW |
| dc.subject | 線性器 | zh_TW |
| dc.subject | 退縮功率附加效率 | zh_TW |
| dc.subject | 自動調整偏壓技術 | zh_TW |
| dc.subject | power amplifier | en |
| dc.subject | 5G | en |
| dc.subject | Ka-band | en |
| dc.subject | linearity | en |
| dc.subject | neutralization | en |
| dc.subject | adaptive-bias | en |
| dc.subject | back-off power-added-efficiency | en |
| dc.subject | linearizer | en |
| dc.title | 應用於5G毫米波通訊系統採用線性器與自動調整偏壓技術及中和技術以優化線性度及效率之CMOS功率放大器 | zh_TW |
| dc.title | 5G Millimeter Wave CMOS Power Amplifiers with Enhanced Linearity Efficiency by Linearizer, Adaptive Bias Neutralization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰(Jeng-Han Tsai),張譽騰(Yi-Teng Chang),楊濠瞬(Hao-Shun Yang) | |
| dc.subject.keyword | 功率放大器,線性度,Ka頻段,5G,線性器,退縮功率附加效率,自動調整偏壓技術,中和技術, | zh_TW |
| dc.subject.keyword | power amplifier,linearity,Ka-band,5G,linearizer,back-off power-added-efficiency,adaptive-bias,neutralization, | en |
| dc.relation.page | 98 | |
| dc.identifier.doi | 10.6342/NTU202003087 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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