利用嵌入式陰影分頁表改善 QEMU 64 位元架構系統模擬效能

Abstract

本篇論文探討在 64 位元系統下,藉由將被模擬系統中部份 64 位元虛擬地址空間嵌入模擬系統之 64 位元虛擬地址空間,進而利用嵌入式陰影分頁表改善 64 位元系統模擬效能的有效性。 根據被模擬系統中 64 位元作業系統所支持的虛擬地址空間大小是否小於模擬系統中可使用之 64 位元虛擬地址空間大小,我們將 64 位元系統模擬分成兩種情況,並分別對這兩種情況設計一套嵌入式陰影分頁表系統。 在 x86-64 系統模擬 AArch64 系統的情境下,我們第一種嵌入式陰影分頁表系統執行 SPEC CINT2006 的效能平均能比 QEMU 快 1.47 倍。我們第二種嵌入式陰影分頁表的系統實做尚未完成,因此在 SPEC CINT2006 十二個 benchmark 中我們的系統只能加速其中五個,且只能比 QEMU 快 1.09 倍。然而我們設計的兩種嵌入式陰影分頁表系統在系統開機的模擬效能都沒有辦法比 QEMU 好。

This thesis investigates the effectiveness of using Embedding Shadow Page Table (ESPT) to improve 64-bit guest architecture emulation performance on 64-bit host system by embedding part of guest virtual address space into host virtual address space. We divide 64-bit system emulation into two cases, restricted case and general case, based on whether the size of 64-bit guest operating system supported virtual address space is smaller than the size of available host virtual address space. We proposed two ESPT system designs for those two cases. In AArch64-to-x86_64 system emulation, our restricted case ESPT system achieves an average speedup of 1.47 on SPEC CINT2006 benchmarks compared with QEMU. Our not yet complete general case ESPT system only improves five out of twelve benchmarks and achieves a speedup of only 1.09. However, neither of our system designs can improve system boot benchmarks.