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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Hung-Han Chen | en |
| dc.contributor.author | 陳泓翰 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:17:46Z | - |
| dc.date.available | 2021-08-25 | |
| dc.date.copyright | 2016-08-25 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-18 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49159 | - |
| dc.description.abstract | 隨著下一代行動通訊(5G)相關之放大器研究與日俱增，由於頻寬的短缺及更高傳輸速率的需求，操作頻率往毫米波發展已成必然的趨勢。
本論文主要分成三部分：第一部分為接收器前端電路之高線性度低雜訊放大器相關研究。此高線性度低雜訊放大器製作於65nm CMOS製程，為了改善頻寬的效率，架構上採用分布式導數疊加方法，藉此以達到高速傳輸的目的。此高線性度低雜訊放大器在36到40兆赫茲系統規格之頻帶內提供足夠增益(20.1.2 dB)、平均雜訊指數(4.87 dB)、改善輸入三階交調截取點(4-6.5 dB)。 第二部分展示了應用於38兆赫茲之增強型 (E-mode) 0.15微米砷化鎵 (GaAs)製程功率放大器並且使用不同匹配方式。由於輸出功率受到閘極漏電流影響，此兩級功率放大器閘極偏壓採用短路截線偏壓(AC-grounded short-stub bias)而不是透過大電阻偏壓方式。此提出之功率放大器於37到39 GHz操作頻率下達到了24.4 dBm 之飽和輸出功率、29.4 %之最大功率附加效率、23.8 dBm 之1dB壓縮輸出功率點，以及提供16.1 dB之小訊號增益。 第三部分同樣是應用於38兆赫茲之空乏型 (D-mode) 0.1微米砷化鎵 (GaAs) 製程功率放大器。此兩級功率放大器採用四路直接功率結合架構來達到瓦特級之輸出功率，於37到40 GHz操作頻率下達到了超過30 dBm之飽和輸出功率、28.5 dBm之1dB壓縮點輸出功率、26.5%之最大功率附加效率，以及提供15.1 dB之小訊號增益。 | zh_TW |
| dc.description.abstract | There are many researches on millimeter-wave frond-end amplifiers for developing 5G wireless systems in recent years. The demands of high-speed internet and the shortage of the bandwidth have motivated the designers to explore millimeter wave (mm-wave) frequency with broader bandwidth for 5G cellular applications.
This thesis is divided into three parts. The first part presents the researches on high linearity low noise amplifiers for RF frond end. This low noise amplifier fabricated in 65-nm CMOS process with distributed derivative superposition (DS) linearization technique is to improve spectral efficiency in the high speed wireless communication systems. This high linearity LNA provides an adequate gain of 21.2 dB and obtains the average noise figure of 4.87 dB in the desired band. Also, the IIP3 of the proposed LNA with linearizer has been improved 4-6.5 dB from 36 to 40 GHz. The second part of the thesis is the proposed PA fabricated in 0.15-µm enhancement mode (E-mode) GaAs PHEMT with different matching methods. Due to the output power influenced by the gate leakage current, the gate bias circuits are bypassed through a AC-grounded short stub rather than through a large resistor. The PA has Psat of 24.4 dBm with 29.4 % PAEmax and OP1dB of 23.8 dBm and provides an adequate gain of 16.1 dB within 37 to 39 GHz. Finally, a 38 GHz power amplifier (PA) using 0.1-µm depletion mode (D-mode) GaAs PHEMT process is reported. Utilizing 4-way direct-combining technique is to achieve watt-level output power in this two-stage PA design. The large-signal performances of the proposed PA achieves Psat of over 30 dBm, better than 26.5 % PAEmax and over 28.2-dBm OP1dB from 37 to 40 GHz. Also, it provides an adequate gain of 15.1 in the desired band. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:17:46Z (GMT). No. of bitstreams: 1 ntu-105-R03942088-1.pdf: 5111443 bytes, checksum: 6c0115eb85783650070de9ff2aa9742f (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 中文摘要 i
ABSTRACT iii CONTENTS v LIST OF FIGURES vii LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 2 1.2.1 Q-band LNAs 2 1.2.2 Q-band PAs 4 1.3 Contributions 7 1.4 Thesis Organization 9 Chapter 2 Design of a 38-GHz LNA in 65-nm CMOS with Distributed Derivative Superposition (DS) Linearization Technique 10 2.1 Introduction 10 2.2 Circuit Design 12 2.2.1 Device Size and Bias Point Selection 12 2.2.2 Circuit Schematic and Simulation 16 2.3 Experimental Results 28 2.4 Summary 32 Chapter 3 Design of a 38-GHz Power Amplifier in 0.15-µm E-mode GaAs PHEMT process 34 3.1 Introduction 34 3.2 Circuits Design 36 3.2.1 Device Size and Bias Point Selection 36 3.2.2 Driver Stage Design 43 3.2.3 Gate Leakage Current 47 3.2.4 Circuits Simulation 54 3.3 Experiment Results 61 3.3.1 Measurement Results 61 3.3.2 Discussion 72 3.4 Summary 78 Chapter 4 Design of a 38-GHz Power Amplifier in 0.1-µm D-mode GaAs PHEMT process 80 4.1 Introduction 80 4.2 Circuit Design 82 4.2.1 Device Size and Bias Point Selection 82 4.2.2 Driver Stage Design 90 4.3 Simulation results 94 4.4 Summary 99 Chapter 5 Conclusions 101 References 103 | |
| dc.language.iso | en | |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | 低雜訊放大器 | zh_TW |
| dc.subject | 線性器 | zh_TW |
| dc.subject | 互補式金屬氧化物半導體 | zh_TW |
| dc.subject | 增強型與空乏型砷化鎵假型高速電子場效電晶體 | zh_TW |
| dc.subject | 5G無線系統 | zh_TW |
| dc.subject | linearizer | en |
| dc.subject | Low noise amplifier | en |
| dc.subject | 5G wire-less systems | en |
| dc.subject | E-mode and D-mode GaAs pHEMT | en |
| dc.subject | CMOS | en |
| dc.subject | power amplifier | en |
| dc.title | 應用於5G無線系統之毫米波低雜訊放大器與增強型和空乏型砷化鎵功率放大器研究 | zh_TW |
| dc.title | Research of Millimeter-wave Low-Noise Amplifier and E-mode and D-mode GaAs Power Amplifiers
for 5G Wireless System Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰(Jeng-Han Tsai),邱煥凱(Hwann-Kaeo Chiou),林坤佑(Kun-You Lin) | |
| dc.subject.keyword | 低雜訊放大器,線性器,互補式金屬氧化物半導體,增強型與空乏型砷化鎵假型高速電子場效電晶體,5G無線系統,功率放大器, | zh_TW |
| dc.subject.keyword | Low noise amplifier,linearizer,CMOS,E-mode and D-mode GaAs pHEMT,5G wire-less systems,power amplifier, | en |
| dc.relation.page | 109 | |
| dc.identifier.doi | 10.6342/NTU201603245 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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