請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49148完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Yu-Wei Chuang | en |
| dc.contributor.author | 莊郁暐 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:17:25Z | - |
| dc.date.available | 2016-08-26 | |
| dc.date.copyright | 2016-08-26 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-19 | |
| dc.identifier.citation | [1] Yun Chai, Jieh Tsorng Wu “A 5.37mW 10b 200MS/s Dual-Path Pipeline ADC,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 462–464
[2] K. Nagaraj, T. R. Viswathan, K. Singhal, and J. Vlach, “Switched-capacitor circuits with reduced sensitivity to amplifier gain,” IEEE Trans. Circuits Syst., vol. CAS-34, no. 5, pp. 571–574, May 1987. [3] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated dual sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [4] B. R. Gregoire and U. Moon, “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620–2630, Dec. 2008. [5] P. J. Lim and B. A. Wooley, “A high-speed sample-and-hold technique using a Miller hold capacitance,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 643–651, Apr. 1991. [6] C.-C. Hsu and J.-T. Wu, “A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier,” in Symp. VLSI Circuits Dig. Tech. Papers, 2003, pp. 263–266. [7] Z.-M. Lee, C.-Y. Wang, and J.-T. Wu, “A CMOS 15-bit 125-MS/s time-Interleaved ADC with digital background calibration,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2149–2160, Oct. 2007. [8] B. Hershberg, S. Weaver, and U. Moon, “Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2623–2633, Dec. 2010. [9] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon, “Ring amplifiers for switched-capacitor circuits,” in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 460–461. [10] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon, “Ring amplifiers for switched capacitor circuits,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2928–2942, Dec. 2012. [11] B. Hershberg and U. Moon, “A 75.9 dB-SNDR 2.96 mW 29 fJ/convstep ringamp-only pipelined ADC,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2013, pp. 94–95. [12] Y. Lim and M. P. Flynn, “A 100 MS/s 10.5 b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers,” IEEE J. Solid-State Circuits, vol. 50, no. 10, pp. 2331–2341, Oct. 2015. [13] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2901–2911, Dec. 2015. [14] A. Chow and H.-S. Lee, “Offset Cancellation for Zero Crossing Based Circuits,” IEEE International Symposium on Circuits and Systems,pp. 1719 – 1722, 2010. [15] L. Brooks and H.-S. Lee, “A zero-crossing-based 8 b 200 MS/s pipelined ADC,” in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 460–615. [16] S.-K. Shin et al., “A fully-differential zero-crossing-based 1.2 V 10b 26 MS/S pipelined ADC in 65 nm CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2008, pp. 218–219. [17] L. Brooks and H.-S. Lee, “A 12 b 50 MS/s fully differential zero crossing-based ADC without CMFB,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 166–167. [18] D.-Y. Chang et al., “A 21 mW 15 b 48 MS/s zero-crossing pipeline ADC in 0.13 m CMOS with 74 dB SNDR,” in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 204–205. [19] T. Oh, H. Venkatram, and U. Moon, “A 70 MS/s 69.3 dB SNDR 38.2fJ/conversion-step time-based pipeline ADC,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2013, pp. C96–C97. [20] T. Oh, H. Venkatram, and U. Moon, “A time-Based pipelined ADC using both voltage and time domain information,” IEEE J. Solid-State Circuits, vol. 49, no.4, pp.961-971, April 2014. [21] Junhua Shen and Peter R. Kinget, “Current-Charge-Pump Residue Amplification for Ultra-Low-Power Pipeline ADCs,” IEEE Trans. Circuits Syst. II, vol. 58, no. 7, pp. 412-416, Jul. 2011. [22] H. Yang and R. Sarpeshkar, “A time-based energy-efficient analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1590–1601, Aug. 2005. [23] M. Lee, M. E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808–2816, Oct. 2009. [24] Younghoon Kim; Changsik Yoo 'A 100-kS/s 8.3-ENOB 1.7-uW Time-Domain Analog-to-Digital Converter', Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 61, no. 6, pp. 408 – 412, June. 2014. [25] Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, and Seung-Tak Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS” IEEE J. Solid-State Circuits, vol. 48, no.6, pp.1429-1441, June. 2013. [26] Miyahara, M., et Al., “22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers,” ISSCC Dig. Tech. Papers, pp. 399-389, Feb. 2014. [27] J.-E. Jang, “Comparator-Based Switched-Capacitor Pipeline ADC with Background offset calibration,” IEEE International Symposium on Circuits and Systems, pp. 253–256, 2011. [28] B. Razavi, “Design of analog CMOS Integrated Circuit” McGRAW-HILL INTERNATIONAL EDITION, August 2000 [29] S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992. [30] S. K. Shin, Jacques C. Rudell, Denis C. Daly, Carlos E. Muñoz, D. Y. Chang, Kush Gulati, H. S. Lee, and Matthew Z. Straayer, ” A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration,” IEEE J.Solid-State Circuits, vol. 49, no. 6, pp. 1366-1381, Jun. 2014 [31] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048–1055, Jul. 2001. [32] O. Stoeble, V. Dias, and C. Schwoerer, “An 80 MHz 10b pipeline ADC with dynamic range doubling and dynamic reference selection,” in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 462–539. [33] T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee,“Comparator-based switched-capacitor circuits for scaled CMOS technologies,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Paper, Feb. 2006, pp. 812–821. [34] Adel Sedra and K.C. Smith, “Microelectronic Circuits”, 5th Edition, Oxford. University Press, International Version, 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49148 | - |
| dc.description.abstract | 本論文提出一個十位元每秒3億次之導管式類比至數位轉換器，為了解決運算放大器在先進製程難以設計並且功率消耗過大，同時時域訊號的解析度於先進製程更加準確，所以設計成利用將電壓訊號轉換成時域訊號來做量化，避開使用運算放大器，並且將電壓相減之部分移動至時域信號相減，以解決比較器之延遲造成之電壓溢出的問題
論文設計之類比至數位轉換器主面積為0.694mm2, 模擬結果可達到9.49的有效位元，同時功率消耗為5.2毫瓦，FoM約為22fJ/conversion-step. 但是因為設計時並沒有考慮好噪音干擾的問題，實際做出來之晶片之有效位元低於5，因此本論文後面會進行有關噪音干擾之分析以及改進方法的討論。 | zh_TW |
| dc.description.abstract | This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid the overshoot problem due to the delay of comparator.
The active area of the proposed work is about 0.694mm2. The ENOB can reach 9.49bit in post-simulation, whose power consumption is 5.2mW and FoM is 22fJ/conversion-step. Unfortunately, the noise of the proposed work was not carefully considered. So, the performance of chip is limited under 5bit. With these problem, the noise analysis and evolve way will be discussed in the thesis. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:17:25Z (GMT). No. of bitstreams: 1 ntu-105-R01943037-1.pdf: 3147948 bytes, checksum: 3c294fc5b5243c3ddcd68a7e397de524 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 I
中文摘要 II ABSTRACT III CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 2 CHAPTER 2 FUNDAMENTALS OF ADC 3 2.1 Introduction 3 2.2 Performance metrics 3 2.2.1 Offset and gain error 3 2.2.2 Differential and integral nonlinearity (DNL and INL) 4 2.2.3 Signal-to-noise ratio (SNR) 5 2.2.4 Total harmonic distortion (THD) 6 2.2.5 Spurious free dynamic range (SFDR) 6 2.2.6 Signal-to-noise and distortion ratio (SNDR) 7 2.2.7 Effective number of bits (ENOB) 7 2.2.8 Figure of merit (FoM) 7 2.3 Architectures of ADC 8 2.3.1 Flash ADC 8 2.3.2 Pipeline ADC 9 2.3.3 SAR ADC 10 2.3.4 Delta-sigma ADC 12 CHAPTER 3 POWER EFFICIENT PIPELINE ADC IN ADVANCED TECHNOLOGY 14 3.1 Opamp-based pipeline ADC 18 3.1.1 Dual path pipeline ADC 18 3.1.2 Ring amplifier pipeline ADC 20 3.2 Opamp-less pipeline ADC 22 3.2.1 Zero crossing based pipeline ADC 22 3.2.2 Time domain pipeline ADC 24 CHAPTER 4 PROPOSED TIME DOMAIN PIPELINE ADC 27 4.1 Concept of the time domain ADC 30 4.1.1 Voltage-to-pulse converter(VPC) 33 4.1.2 Pulse-to-voltage converter(PVC) 35 4.1.3 Delay time cancellation 36 4.1.4 Architecture 38 4.1.5 Dual sampling 43 4.1.6 Residue plot 46 4.2 Circuit implementation 50 4.2.1 Current source 51 4.2.2 Comparator 56 4.2.3 Sub-TDC 60 4.2.4 Clock generator 61 4.3 Noise analysis 62 4.3.1 KT/C noise 63 4.3.2 Current source noise 63 4.3.3 Comparator noise 64 4.4 Noise calculation and simulation 66 4.4.1 calculation of KT/C noise 66 4.4.2 calculation of current source noise 67 4.4.3 calculation of comparator noise 67 4.4.4 simulation result of noise 71 CHAPTER 5 SIMULATION AND MEASUREMENT 76 5.1 Simulation results 76 5.1.1 pre-simulation result 77 5.1.2 post-simulation result 83 5.2 Measurement environment 87 5.2.1 Chip layout 87 5.2.2 Measurement setup 90 5.2.3 PCB design 92 5.3 Measurement results 95 CHAPTER 6 CONCLUSION AND FUTURE WORK 99 REFERENCE 108 | |
| dc.language.iso | en | |
| dc.subject | 比較器 | zh_TW |
| dc.subject | 噪音干擾 | zh_TW |
| dc.subject | 電壓溢出 | zh_TW |
| dc.subject | 時域訊號 | zh_TW |
| dc.subject | 導管式類比至數位轉換器 | zh_TW |
| dc.subject | noise | en |
| dc.subject | comparator | en |
| dc.subject | pipeline ADC | en |
| dc.subject | overshoot | en |
| dc.subject | time domain | en |
| dc.title | 一個利用時間軸轉換技巧的低功率導管式類比數位轉換器 | zh_TW |
| dc.title | A Low Power Pipeline ADC Using Time-Domain Transfer Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成,蔡宗亨 | |
| dc.subject.keyword | 導管式類比至數位轉換器,時域訊號,比較器,電壓溢出,噪音干擾, | zh_TW |
| dc.subject.keyword | pipeline ADC,time domain,comparator,overshoot,noise, | en |
| dc.relation.page | 112 | |
| dc.identifier.doi | 10.6342/NTU201603020 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-105-1.pdf 未授權公開取用 | 3.07 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。