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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Charlie Chung-Ping Chen) | |
| dc.contributor.author | Yi-Ting Chen | en |
| dc.contributor.author | 陳奕廷 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:10:18Z | - |
| dc.date.available | 2019-02-08 | |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-09-28 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48853 | - |
| dc.description.abstract | 本論文中提出了一種實現高速低功率逐漸趨近式類比數位轉換器的技術，並且透過實際的晶片下線與實際量測驗證。此逐漸趨近式類比數位轉換器使用的非同步預先重置以及雙路徑快速切換技術可以有效地提升電路的操作速度。所提出的電路設計技術以及晶片實作成果簡述如下：
本設計使用台積電90奈米製程製作，實現一個10位元、1.58mW、每秒一億次取樣的逐漸趨近式類比數位轉換器。雙路徑快速切換技術能夠有效縮短決定時間並大幅改善操作速度，非同步預先重置技術於第一時間將電容上不需要的電荷清除，可提升操作頻率。量測結果在操作頻率為10MS/s時，輸入頻率1MHz下ENOB和SFDR為9.10位元和76.53dB，輸入頻率為Nyquist-rate時ENOB和SFDR為9.13位元和75.50dB；在取樣頻率為20MS/s時，輸入頻率1MHz下ENOB和SFDR為9.03位元和74.32dB，輸入頻率為Nyquist-rate時ENOB和SFDR為9.01位元和69.84dB；當取樣頻率為50MS/s，輸入頻率為2MHz時，ENOB和SFDR為8.4和66.68dB；輸入頻率為20MHz時，ENOB和SFDR為8.25和66.39dB；而在操作頻率為100MS/s，輸入頻率為2MHz時，ENOB和SFDR為8.20和59.36dB；W輸入頻率為Nyquist-rate時，ENOB和SFDR為7.30和55.81dB。同時在100MS/s的操作頻率且1伏特的操作電壓時，其功率消耗為1.58mW。FoM在2MHz和50MHz輸入頻率下分別為51fJ/conversion-step和99fJ/conversion-step。 | zh_TW |
| dc.description.abstract | This thesis proposes a high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). The dual path fast-switching and asynchronous resetting method effectively improve the operating speed of SAR ADC. Following shows the proposed methods and measurement results.
A 10-bit 100MS/s 1.58mW SAR ADC with the novel methods is implemented in TSMC 90nm CMOS technology. The dual path fast-switching method shortens the decision time and dramatically improves operating speed of the ADC. The asynchronous resetting method clears the unnecessary charges on capacitors as soon as possible. In measurement results, when the SAR ADC operates at 10MS/s sampling rate with Nyquist-rate input frequency, the measured ENOB and SFDR is 9.13 and 75.50dB. At 20MS/s sampling rate with Nyquist-rate input frequency, the measured ENOB and SFDR is 9.01 and 69.84dB. At 50MS/s sampling rate with 2MHz input frequency, the measured ENOB and SFDR is 8.40 and 66.68dB. With 20MHz input frequency, the measured ENOB and SFDR is 8.25 and 66.39dB. At 100MS/s sampling rate with 2MHz input frequency, the measured ENOB is 8.20 and SFDR is 59.36dB. The ADC consumes 1.58mW from 1-V supply when the sampling rate is 100MS/s, the resulting figure of merit (FOM) is 51fJ/conversion-step at 2MHz input frequency, and 99fJ/conversion-step at 50MHz input frequency. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:10:18Z (GMT). No. of bitstreams: 1 ntu-105-R02943132-1.pdf: 8471360 bytes, checksum: e0bc31fc1f28e2543145b1df74100b5a (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 I 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamental of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 ADC Performance metrics 3 2.2.1 Differential Nonlinearity (DNL) 3 2.2.2 Integral Nonlinearity (INL) 4 2.2.3 Signal to Noise Ratio (SNR) 5 2.2.4 Signal-to-(Noise + Distortion) Ratio (SNDR) 7 2.2.5 Resolution and Effective Number of Bits (ENOB) 8 2.2.6 Spurious-Free Dynamic Range (SFDR) 8 2.2.7 Figure of Merit (FoM) 9 2.3 Architectures of Analog-to-Digital Converters 9 2.3.1 Flash ADC 10 2.3.2 Two Step and Sub-Ranging ADC 12 2.3.3 Pipelined ADC [6] 13 2.3.4 Cyclic ADC 14 2.4 Basic SAR ADC introduction 17 2.4.1 Introduction 17 2.4.2 Basic SAR ADC 18 Chapter 3 The Proposed High Speed and Low Power SAR ADC 21 3.1 Introduction 21 3.2 Proposed SAR ADC 22 3.2.1 Conventional SAR ADC 22 3.2.2 Monotonic SAR ADC 24 3.2.3 Architecture of Proposed SAR ADC 25 3.3 Circuit Implementation 29 3.3.1 Sampling switch 29 3.3.2 Comparator 32 3.3.3 Tunable Delay Circuit 35 3.3.4 Master slave D Flip-Flop with Clocked Inverters 36 3.3.5 SAR Logic with asynchronous resetting method 38 3.3.6 Capacitor array 39 3.4 Layout and Simulation Results 41 3.4.1 Pre-simulation Results 41 3.4.2 Post-simulation Results 44 3.4.3 Layout Implementation 46 3.4.4 Summary 48 3.5 Experimental Results 49 3.5.1 Introduction 49 3.5.2 Measurement Environment setup 50 3.5.3 PCB Layout 51 3.5.4 Measurement Result 53 3.6 Summary 62 Chapter 4 Conclusion and Future Work 64 4.1 Conclusions 64 4.2 Future work 64 Reference 66 | |
| dc.language.iso | en | |
| dc.subject | 逐漸趨近式類比至數位轉換器 | zh_TW |
| dc.subject | 十位元 | zh_TW |
| dc.subject | SAR ADC | en |
| dc.subject | Successive-Approximation Register Analog-to-Digital Converters | en |
| dc.title | 一個90奈米1.58mW十位元每秒取樣一億次的逐漸趨近式類比至數位轉換器設計 | zh_TW |
| dc.title | A 10-bit 100MS/s 1.58mW Successive-Approximation Register Analog-to-Digital Converters in 90 nm CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),陳巍仁(Wei-Ren Chen),張順志(Soon-Jyh Chang) | |
| dc.subject.keyword | 逐漸趨近式類比至數位轉換器,十位元, | zh_TW |
| dc.subject.keyword | SAR ADC,Successive-Approximation Register Analog-to-Digital Converters, | en |
| dc.relation.page | 67 | |
| dc.identifier.doi | 10.6342/NTU201603606 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-09-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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