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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北 | |
| dc.contributor.author | Yi-Jyun Lee | en |
| dc.contributor.author | 李宜峻 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:09:54Z | - |
| dc.date.available | 2017-02-08 | |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-10-07 | |
| dc.identifier.citation | [1] M. Vai and S. Prasad, “Automatic impedance matching with a neural network,”IEEE Microwave Guided Wave Lett., vol. 3, no. 10, pp.353–354, Oct. 1993.
[2] V. K. Devabhaktuni, C. Xi, F. Wang, and Q. J. Zhang, “Robus t training of microwave neural models,”IEEE MTT-S Int. Microwave Symp. Dig., Anaheim, CA,June 1999, pp. 145–148. [3] F. Wang, V. K. Devabhaktuni, and Q. J. Zhang, “A hierarchical neural network approach to the development of a library of neural models for microwave design,” IEEE Trans. Microwave Theory Tech., vol. 46, pp.2391–2403, Dec. 1998. [4] P. M. Watson, K. C. Gupta, “EM-ANN models for Microstrip Vias and Intreconnects in Dataset Circuits,” IEEE Trans., Microwave Theory Tech., Vol. 44, No-12, 1996, pp.2495-2503. [5] K.-T. Hsu, W.-D. Guo, G.-H. Shiue, C.-M. Lin, T.-W. Huang, and R.-B. Wu, “Design of reflectionless vias using neural network-based approach,” IEEE Trans. Adv. Packag., vol. 31, no. 1, pp. 211–218, Feb.2008. [6] W. T. Beyene, “Application of artificial neural networks to statistical analysis and nonlinear modeling of high-speed interconnect systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 1, pp. 166–176, Jan. 2007. [7] Veluswami, M. S. Nakhla and Q.-J. Zhang, 'The application of neural networks to EM simulation and optimization of interconnects in high-speed VLSI circuits,' IEEE Trans. Microwave Theory Tech., vol. 45, pp. 713-722, May 1997. [8] Martin T. Hagan , Howard B. Demuth , Mark Beale, Neural network design. PWS Publishing Co., Boston, MA, 1997, ch.2 [9] 蘇木春、張孝德.機器學習：類神經網路、模糊系統以及基因演算法, 全華科技圖書, ch.3,4 [10] Cheng, D. K.. Field and wave electromagnetics. Reading, Mass: Addison Wesley.1983, ch.9 [11] Stephen H. Hall , Howard L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, Wiley-IEEE Press, 2009, ch.13 [12] J. de Villiers and E. Barnard, “Backpropagation neural nets with one and two hidden layers,” IEEE Trans. Neural Networks, vol. 4, pp. 136–141,Jan. 1992. [13] S. Xu and L. Chen, “A novel approach for determining the optimal number of hidden layer neurons for FNN's and its application in data mining,” Proc. 5th ICITA, 2008, pp. 683–686. [14] W. -C. Chen, C. -P. Chang, M. -K. Kang, T. -U. Huang, K. -B. Wu and R. -B. Wu,'Artificial neural network modeling for Extrinsic capacitance of FinFET,' 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems,Portland, OR, 2014, pp. 95-98. [15] JMP® , Version 10. SAS Institute Inc., Cary, NC, 1989-2007. [16] Labs, X.-b. 'Memory System.' from http://www.xbitlabs.com/articles/memory/. [17] J.G. Proakis, Digital communications, McGraw-Hill, Boston, 2001. [18] H.-H. Chuang, W.-D. Guo, Y.-H. Lin, H.-S. Chen, Y.-C. Lu, Y.-S. Cheng, R.-B. Wu, et al., “Signal/power integrity modeling of high-speed memory modules using chip-package-board coanalysis,” IEEE Trans. Electromag. Compat., vol. 52, no. 2, pp.381–391, May 2010. [19] J. Yonggang, X. Baraton, S.w. Yoon, L. Yaojian, Pc. Marimuthu, 'Next Generation eWLB (Embedded Wafer Level BGA) Packaging,'. in Proc. EPTC, Singapore 2010. [20] C.C. Liu, S.M. Chen, F.W. Kuo, H.N. Chen, E.H. Yeh, C.C. Hsieh, et al.,'High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,' IEDM '12, pp. 14.1.1-14.1.4. [21] 'LPDDR4 specification,JESD209-4, JEDEC Standard (2014, Aug.).' from http://www.jedec.org. [22] 郭宗益(June ,2016 ). 改善晶圓級封裝電源完整度之雙層電源接地網格佈局優化法, 台灣大學碩士論文. [23] S. Sousa, F. Martins, M. Alvimferraz, M. Pereira,” Multiple linear regression and artificial neural networks based on principal components to predict ozone concentrations,” Environ. Model. Softw. 22 (2007) 97–103 [24] Sathe PM, Venitz J. “Comparison of neural network and multiple linear regression as dissolution predictors,” Drug Dev. Ind. Pharm. 2003;29:349–355 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48827 | - |
| dc.description.abstract | 本篇論文提出以類神經網路架構，輔助分析記憶體匯流排中設計參數和其眼圖表現的非線性映射函數，並經由此函數找到最佳化設計。本論文利用這個方法在兩種不同的記憶體匯流排架構上做分析，第一種為工業界在第二代雙倍數據率同步動態隨機存取記憶體的位址/控制匯流排一對八的訊號傳輸設計，我們也嘗試利用類神經網路的輔助分析方式，用較高的自由度去設計此電路系統，但成效不高，最後我們使用電路面向去分析電路，用等效電路去探討最佳設計結果的原因。雖然如此，訓練完成的類神經網路能夠快速地對於同樣電路的不同需求，提出完整的設計方針。發現當此架構總長度不長時(<0.3λ)，只需要將特徵阻抗提高來補償電容效應即可。
在第二種架構中，我們分析晶圓級封裝中，用於行動通訊硬體上的低功率雙倍數據率同步動態隨機存取記憶體第四代架構，運用類神經網路分析在下層重新分佈製程線路中的傳輸線尺寸設計，在不同的設計結構上，分析其表現並探討參數改變對於結果的影響，最後同樣以等效電路方式來印證分析結果。 | zh_TW |
| dc.description.abstract | In this thesis, we make use of Artificial Neural Network (ANN) approach to analyze the relation between design parameters and eye diagram performance of memory bus. Then we used the trained ANN function to find the optimal design for two kinds of memory structure. One is the one-to-eight CMD/ADDR/CNTR buses in flyby structure in DDR2 (Double-Data-Rate Two Synchronous Dynamic Random Access Memory).With ANN, we tried to design the structure in higher degree of freedom, but it didn’t help us to get much higher performance results. Therefore, we utilize the equivalent circuit to investigate the key point that effects the performance. Nevertheless, well-trained ANN can quickly suggest the design guideline for different demand in same structure. We find that when the total length of the flyby structure is not long (<0.3λ),it is easy to approach optimal design by letting the characteristic impedance higher.
For another one we analyze the Low Power DDR4 (LPDDR4) transmission line design in the lower redistribution layer in InFO-WLP (Integrated Fan-Out Wafer-Level-Packaging) technology used for mobile devices with ANN. In different kinds of unit cell, we analyze the effect of design parameters on the performance and finally use the equivalent circuit to certify our result. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:09:54Z (GMT). No. of bitstreams: 1 ntu-105-R03942006-1.pdf: 4056880 bytes, checksum: 0092f7e79d26cc94fe0dcdca1441c4bf (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 口試委員會審定書 I
致謝 II 摘要 III 目錄 V 第一章 緒論 1 1.1. 研究動機 1 1.2. 文獻回顧 3 1.3. 主要貢獻 5 1.4. 章節內容概述 5 第二章 理論 7 2.1. 類神經網路簡介 7 2.2. 類神經網路架構與工作原理 8 2.2.1. 類神經元結構 9 2.2.2. 類神經元網路結構 [9] 9 2.3. 誤差倒傳遞演算法 13 第三章 利用類神經網路分析微帶線 19 3.1. 微帶線基本原理 19 3.2. 類神經網路分析流程設計 21 3.2.1. 類神經網路架構參數設計 21 3.2.2. 取樣法則 24 3.3. 微帶線分析流程與結果 27 3.3.1. 設計參數與範圍 27 3.3.2. 訓練與結果比較 28 3.4. 應用:設計低損耗耦合傳輸線 30 第四章 以類神經網路分析DDR一對八匯流排 35 4.1. 記憶體與匯流排結構介紹 35 4.1.1. DRAM記憶體 35 4.1.2. 一對八匯流排結構 37 4.2. 飛越結構最佳化設計 40 4.2.1. 分析流程 40 4.2.2. 類神經網路訓練與測試 45 4.2.3. 最佳化結果 46 4.2.4. 複雜化飛越架構分析 48 4.3. 設計解空間與電路分析 51 第五章 以類神經網路分析晶圓級封裝重新分配層架構 55 5.1. 晶圓封裝技術簡介 55 5.2. LPDDR4與系統電路簡介 57 5.3. 資料線匯流排於下層分配層架構分析 59 5.3.1. 單位傳輸結構介紹 59 5.3.2. 類神經網路訓練與測試結果 61 5.3.3. 參數分析結果 63 第六章 結論 72 參考文獻 73 | |
| dc.language.iso | zh-TW | |
| dc.subject | 記憶體匯流排 | zh_TW |
| dc.subject | 類神經網路 | zh_TW |
| dc.subject | 訊號完整度 | zh_TW |
| dc.subject | 眼圖 | zh_TW |
| dc.subject | 晶圓級封裝 | zh_TW |
| dc.subject | Wafter-Level Package | en |
| dc.subject | Artificial Neural Network | en |
| dc.subject | Memory Bus | en |
| dc.subject | Signal Integrity | en |
| dc.subject | Eye diagram | en |
| dc.title | 利用類神經網路於記憶體匯流排之訊號完整度分析 | zh_TW |
| dc.title | Signal Integrity Analysis on Memory Bus Design with the
Neural Network-Based Approach | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王文山,吳宗霖,洪子聖,鍾世忠 | |
| dc.subject.keyword | 類神經網路,訊號完整度,眼圖,晶圓級封裝,記憶體匯流排, | zh_TW |
| dc.subject.keyword | Artificial Neural Network,Signal Integrity,Eye diagram,Wafter-Level Package,Memory Bus, | en |
| dc.relation.page | 75 | |
| dc.identifier.doi | 10.6342/NTU201603654 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-10-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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