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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.author | Po-Fan Hou | en |
dc.contributor.author | 侯柏帆 | zh_TW |
dc.date.accessioned | 2021-06-15T11:09:50Z | - |
dc.date.available | 2017-02-08 | |
dc.date.copyright | 2017-02-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-10-14 | |
dc.identifier.citation | [1] J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. Campbell, and J. Berech, “Scan-based transition fault testing – Implementation and low cost test challenges,” in Proceedings of IEEE International Test Conference, 2002, pp. 1120–1129.
[2] P. Girard, N. Nicolici, and X. Wen, Eds., Power-Aware Testing and Test Strategies for Low Power Devices. Springer, 2009. [3] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “Low-capture-power test generation for scan-based atspeed testing,” in Proceed-ings of IEEE International Test Conference, 2005, pp. 1019–1028. [4] X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard, Y. Ohsumi, and L.-T. Wang, “A novel scheme to reduce power supply noise for high quality at-speed scan testing,” in Proceedings of IEEE International Test Conference, 2007, paper 25.1. [5] J. Lee and M. Tehranipoor, “LS-TDF: Low-switching transition delay fault pattern generation,” in Proceedings of IEEE VLSI Test Symposium, 2008, pp. 227–232. [6] Y.-H. Li, W.-C. Lien, I.-C. Lin, and K.-J. Lee, “Capture-power-safe test pattern determination for at-speed scan-based testing,” IEEE Transactions on Comput-er-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, January 2014, pp. 127–138. [7] T. Zhang, and D. M. Walker, “Power Supply Noise Control in Pseudo Functional Test,” in Proceedings of IEEE VLSI Test Symposium, 2013, pp. 1-6. [8] N. Ahmed, M. Tehranipoor, and V. Jayaram, “Transition delay fault test pattern generation considering power supply noise in a SoC design,” in Proceedings of the Design Automation Conference, 2007, pp. 533–538. [9] X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, and K. K. Saluja, ”Criti-cal-path-aware X-filling for effective IR-drop reduction in at-speed scan testing,” in Proceedings of the Design Automation Conference, 2007, pp. 527–532. [10] J. Lee, S. Narayan, M. Kapralos, and M. Tehranipoor, “Layout-aware, IR-drop tol-erant transition fault pattern generation,” in Proceedings of Design, Automation & Test in Europe, 2008, pp. 1172-1177. [11] X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. A. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor, “Power-aware test generation with guaranteed launch safety for at-speed scan testing,” in Proceedings of IEEE VLSI Test Symposium, 2011, pp. 166–171. [12] X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, and L.-T. Wang, “On pinpoint capture power management in at-speed scan test generation,” in Proceedings of IEEE International Test Conference, 2012, paper 12.1. [13] S.M. Saeed and O. Sinanoglu, “Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing,” in Proceedings of IEEE VLSI Test Symposium, VOL. 22, NO. 3, March 2014. [14] J. Ma, J. Lee, and M. Tehranipoor, “Layout-aware pattern generation for maximiz-ing supply noise effects on critical paths,” in Proceedings of IEEE VLSI Test Sym-posium, 2009, pp. 221–226. [15] F. Yuan, X. Liu, and Q. Xu, “Pseudo-functional testing for small delay defects con-sidering power supply noise effects,” in IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, 2011, pp. 34–39. [16] L.-C. Tsai, J.-Z. Li, Y.-T. Lin, J.-L. Huang, A. Shih, and Z. F. Conroy,“An IR-drop guided test pattern generation technique,” in Proceedings International Symposium on VLSI Design, Automation and Test, 2016, pp. 1–4. [17] T. Zhang and D. M. Walker, “Improved power supply noise control for pseudo functional test,” in Proceedings of IEEE VLSI Test Symposium, 2014, pp. 1-6. [18] M.-F. Wu, H.-C. Pan, T.-H. Wang, J.-L. Huang, K.-H. Tsai, and W.-T. Cheng, “Im-proved weight assignment for logic switching activity during at-speed test pattern generation,” in Proceedings of the Asia and South Pacific Design Automation Conference, 2010, pp. 493–498. [19] S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz, and J. Rajski, “Pre-ferred Fill: A scalable method to reduce capture power for scan based designs,” in Proceedings of IEEE International Test Conference, 2006, paper 32.2. [20] L. T. Wang, C. W. Wu, and X. Wen, (Editors), “VLSI Test Principles and Architec-tures: Design for Testability,” 2006. [21] A. Chandra and R. Kapur, “Bounded Adjacent Fill for Low Capture Power Scan Testing,” in Proceedings of IEEE VLSI Test Symposium, 2008, pp. 131-138. [22] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” in Proceedings of IEEE International Test Conference, 2005, pp. 265-270. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48822 | - |
dc.description.abstract | 在測試模式下,過多的信號轉換動作(switching activity)會降低電路效能(circuit performance),導致良好的晶片未通過測試,造成良率損失。本篇論文提出了一考慮壓降的測試圖樣(test pattern)產生方式—MIR-fill來產生高測試品質(test quality)的圖樣。藉由控制信號的轉換動作,使測試圖樣在電路中的壓降分布(IR-drop dis-tribution)匹配(match)使用者定義的壓降分布。實驗結果顯示利用此技術產生的測試圖樣,其壓降分布與使用者定義之壓降分布相似,且維持測試圖樣數量以及錯誤涵蓋率,並較先前研究加速了18倍。 | zh_TW |
dc.description.abstract | The excessive circuit switching activity during scan-based at-speed testing has been known to cause yield loss because it degrades the circuit performance and can cause a good device to fail the test. In this thesis, we propose an IR-drop aware test pattern generator to produce high-quality at-speed test patterns. The idea is to manage the switching activity distribution of the generated test patterns so that the resulting IR-drop profiles match the user-specified ones. To improve the efficiency of the IR-drop matching process, the maximum-implication random-fill (MIR-fill) based IR-drop matching technique is developed. Simulation results show that the proposed test pattern generator generates test patterns with high similarity IR-drop distribution to user-specified one and also achieves 18 times speedup compared to the previous work. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T11:09:50Z (GMT). No. of bitstreams: 1 ntu-105-R03943098-1.pdf: 2469665 bytes, checksum: f91912321c410e0a8fdded02d07f448b (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv TABLE OF CONTENTS v LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Previous Works 1 1.2 Motivation 3 1.3 Contribution 4 1.4 Thesis Organization 5 Chapter 2 Preliminaries 6 2.1 At-Speed Scan Test 6 2.2 Estimation of IR-Drop Distribution 8 2.2.1 Reduced IR-Drop Profile 8 2.2.2 Reduced Cost Function of IR-Drop Profile Difference 9 2.2.3 Representative Functional Pattern (RFP) 10 Chapter 3 Proposed IR-Drop Aware Test Pattern Generator 11 3.1 Overall Flow 12 3.2 Choice of X-Fill Techniques 13 3.2.1 Low Implication Efficiency of Random-Fill 14 3.3 Relation Based Input Grouping 16 3.3.1 Input Relation 17 3.3.2 Weighted Input Relation (WIR) 18 3.3.3 Normalized Weighted Input Relation (NWIR) 19 3.3.4 Input Partitioning 21 3.4 Maximum-Implication Random-Fill (MIR-fill) Based IR-Drop Matching 23 3.4.1 Reduced Cost Function of IR-Drop Distribution with X-bits 24 3.4.2 Test Cube Generation 24 3.4.3 Target Group Selection 24 3.4.4 Multi-Random-Fill 30 3.4.5 Bit Flipping 31 Chapter 4 Experiment Results 33 4.1 MIR-Fill Experiment Result 34 4.2 Compare with Other Algorithms 37 4.2.1 Compare with Baseline TPG 44 4.2.2 Compare with [16] 56 4.3 Validate Effectiveness of Functions 58 4.3.1 Target Group Selection 58 4.3.2 Acceptance Threshold Voltage 59 4.3.3 Group Size 60 Chapter 5 Conclusion 63 REFERENCE 64 | |
dc.language.iso | en | |
dc.title | 匹配壓降分布之訊號傳遞效率最佳化填充以提升全速掃描鏈測試品質 | zh_TW |
dc.title | MIR-Fill Based IR-Drop Profile Matching to Improve At-Speed Scan Test Quality | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂學坤,李進福,黃炫倫 | |
dc.subject.keyword | 全掃描,全速測試,測試品質,良率損失,壓降,測試耗能管理,最佳邏輯值傳遞效率填充, | zh_TW |
dc.subject.keyword | full scan,at-speed testing,test quality,yield loss,IR-drop,test power management,maximum-implication-random-fill, | en |
dc.relation.page | 66 | |
dc.identifier.doi | 10.6342/NTU201603638 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-10-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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