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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48325完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | |
| dc.contributor.author | Yu-Cheng Hung | en |
| dc.contributor.author | 洪裕程 | zh_TW |
| dc.date.accessioned | 2021-06-15T06:52:37Z | - |
| dc.date.available | 2015-02-20 | |
| dc.date.copyright | 2011-02-20 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-02-14 | |
| dc.identifier.citation | [1] J. G. Maneatiss, “Low-Jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[2] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1st Ed., McGraw-Hill, 2001. [3] B. Razavi, 'Design of Integrated Circuits for Optical Communications,” 1st Ed., Mc-Graw Hill, 2003. [4] J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, and C. Kim, “A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling” IEEE J. Solid-State Circuits, vol. 41, pp. 2077-2082, Sep. 2006. [5] H. Jin, and E. K. F. Lee, “A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC’s,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 7, pp. 603-613, Jul. 2000. [6] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS Data Recovery DLL Using Half-Frequency Clock,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 711-715, Jun. 2002. [7] A. L. Coban, M. H. Koroglu, and K. A. Ahmed, “A 2.5-3.125-Gb/s Quad Transceiver With Second-Order Analog DLL-Based CDRs,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1940-1947, Sep. 2005. [8] R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J. Edward Lee, R. Rathi and J. Poulton, “A Low-Power Multiplying DLL for Low-Jitter Multigiga hertz Clock Generation in Highly Integrated Digital Chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, Dec. 2002. [9] T. Matano et al., “A 1-Gb/s/pin 512-Mb DDRII SDRAM Using a Digital DLL and a Slew-Rate-Controlled Output Buffer,” IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 762-768, May 2003. [10] J. J. Kim, S.-B. Lee, T.-S. Jung, C.-H. Kim, S.-I. Cho, and B. Kim, “A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1430-1436, Oct. 2000. [11] S. Tanoi, T. Tanabe, K. Takahashi, S. Miyamoto, and M. Uesugi, “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture,” IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 487-493, Apr. 1996. [12] S. Eto, M. Matsumiya et al., “A 1 Gb SDRAM with ground level precharged bitline and nonboosted 2.1 V word line,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, Feb. 1998, pp. 82-83. [13] A. Hatakeyama et al., “A 256 Mb SDRAM using a register-controlled digital DLL,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, Feb.1997, pp. 72-73. [14] T-C Lee and K-J Hsiao, “The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application,” IEEE Journal of Solid-State Circuits, pp. 1245-1252, Jun. 2006. [15] J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, pp. 62-40, Feb. 1989. [16] J. Cao et al., “OC-192 Reciver in Standard 0.18-μm CMOS,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 187-188, Feb. 2002. [17] J. C. Scheytt, G. Hanke and U. Langmann, “A 0.155, 0.622, and 2.488 Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate Transparent SDH Systems,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 348-349, Feb. 1999 [18] A. X. Widmer and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM J. Res. And Develop., vol. 27, pp. 440-451, Sept. 1983. [19] C. Hogge, “A self-correcting clock recovery circuit,” IEEE Journal of Light wave Technology, vol. LT-3, pp 1312-1314, Dec. 1985. [20] J. D .H. Alexander, “Clock Recovery from Random Binary Data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975. [21] J. Lee, Kenneth S. Kundert and B. Razavi, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1571-1580, Sept. 2004. [22] A. Pottbacker, U. Langmann and H. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992. [23] R. J. Yang, S. P. Chen and S. I. Liu, “A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet,” IEEE Journal of Solid-State Circuits, pp. 1356-1360, Aug. 2004. [24] K. Kishine, K. Ishii and H. Ichino, “Loop-Parameter Optimization of a PLL for a Low-Jitter 2.5-Gb/s One-Chip Optical Receiver IC With 1:8 DEMUX,” IEEE Journal of Solid-State Circuits vol. 37, pp. 38-50, Jan. 2002. [25] P. Trischitta and E. Varma, “Jitter in Digital Transmission Systems,” Norwood, MA: Artech House, 1989. [26] S. K. Mitra, “Digital Signal Processing: A Computer-Based Approach,” New York: McGraw-Hill, 2001. [27] V. Kratyuk et al., “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 3, pp. 247-251, Mar. 2007. [28] P. Andreani. “More on the 1/f2 Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillator,” IEEE Journal of Solid-State Circuits, pp. 2703-2712, Jan. 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48325 | - |
| dc.description.abstract | 本篇論文包含兩個已執行在標準CMOS製程的積體電路晶片，一個是延連鎖相迴路，另一個是時脈資料回復電路。
延連鎖相迴路已經被廣泛的利用在高速記憶體介面電路和時脈倍頻器和多相位時脈產生器以及用來去時脈的偏斜.比起傳統的相位鎖定迴路，延連鎖相迴路有兩個主要的優點。第一個是快速鎖定，另一個是無條件穩定。在些論文的前半部分，提出的是一個任意寬域延遲去偏斜時脈產生器，輸入頻率為300到800百萬赫茲。此延連鎖相迴路在0.18微米中實現。並達到低抖動、低功率消耗、低面積之特性。 隨著資料傳輸的快速發展，在超過好幾十億赫茲操作速率的通訊系統要求更低的成本。傳輸的介質資也因為追求更高的頻寬逐漸的從銅線演變成光纖。時脈資料回復電路移除資料的抖動並回復資料給接下來的電路使用。在這個研究主題中從數位電路的的觀點詳盡的介紹研究和電路的實現。 後半部分論文提出一個基於時間數位轉換器而設計的全數位寬追蹤範圍的時脈資料回復電路並於在90奈米中實現。些架構大大的增加了捕獲範圍。 | zh_TW |
| dc.description.abstract | This thesis contains two chips one is DLL the other is CDR implemented in standard CMOS technology.
The delay locked loop (DLL) is widely used for high-speed memory interface circuits and clock multipliers to perform clock de-skew. The DLL offers two attractive advantages over conventional PLL: one is a faster locked time, and the other is unconditionally stability. First, half of this thesis proposed a 300- to 800-MHz low jitter and ringing effect free de-skew clock generator for arbitrary delay. The generator is designed and fabricated in a 0.18-μm CMOS process. The power consumption is 10mW at 800MHz. The rapid growth of data transmission demands low-cost communication systems operating at frequencies over several GHz. The pursuit for larger bandwidth converts the transmission medium from copper wire to fiber gradually. Clock and data recovery (CDR) circuits both remove the jitter in the data and retime the data for the succeeding circuits. A complete investigation and implementation of this CDR from a digital circuit point of view will be elaborated in this research. The other half of this thesis proposed a TDC-based all-digital wide capture range CDR and is implemented by standard 90-nm CMOS technology. The proposed architecture can increase the capture range. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T06:52:37Z (GMT). No. of bitstreams: 1 ntu-100-R97943134-1.pdf: 7851094 bytes, checksum: 58f8dde097a45421c5b1ffe8f3509aed (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 摘要 iii
Abstract iv Contents v List of Figures ix List of Tables xiii Chapter 1 Thesis Overview 1 Chapter 2 Introduction of DLL 3 2.1 Basic Concepts of DLL 3 2.1.1 Delay locked Loop (DLL) 3 2.1.2 Phase Detector (PD) 4 2.1.3 Charge Pump (CP) 6 2.1.4 Voltage Control Delay Line (VCDL) 7 2.1.5 Transfer Function 9 2.1.6 Jitter 11 2.1.7 Noise 12 2.2 Applications 14 2.2.1 Multiphase Clock Generation 14 2.2.2 Frequency Multiplication 18 2.2.3 Clock Synchronization 19 Chapter 3 A 300- to 800-MHz De-skew Clock Generator for Arbitrary Delay 21 3.1 Motivation 21 3.2 Conventional Architecture and the Analyses 22 3.2.1 Conventional Architecture 22 3.2.2 The analysis 24 3.2.3 Stability limits - Root locus method 25 3.2.4 Design constraint 27 3.3 Proposed Architecture and the Analyses 27 3.3.1 Proposed architecture 27 3.3.2 The simulation of settling time 28 3.3.3 The analysis 29 3.4 Circuit Implementation 33 3.4.1 Voltage Control Delay Line and Dummy 33 3.4.2 Phase selector 34 3.4.3 Charge Pump 35 3.4.4 Phase Detector 36 3.5 Die Photo, Floor Plan and Pad 37 3.6 Experimental Results 39 3.6.1 Test Equipments 39 3.6.2 Experimental Results 40 3.7 Conclusion 43 Chapter 4 Introduction of CDR 45 4.1 Introduction 45 4.1.1 Receivers Building Block 45 4.1.2 Universal Serial Bus 3.0 (USB 3.0) 46 4.1.3 Clock and Data Recovery (CDR) 47 4.2 Basic Concepts of CDR 49 4.2.1 Properties of Random Binary Data 49 4.2.2 Phase Detector of Random Data (PD) 51 4.2.3 Frequency Detector of Random Data (FD) 56 4.3 Performance of CDR Specification 60 4.3.1 Jitter transfer 60 4.3.2 Jitter tolerance 61 4.3.3 Jitter generation 62 4.3.4 Eye Diagram 62 Chapter 5 An All-Digital Continuous Rate Wide-Capture Range CDR 65 5.1 Motivation 65 5.2 Proposed Architecture 66 5.2.1 Architecture 66 5.2.2 Time to Digital Converter (TDC) 68 5.2.3 Grab minimum data pulse 69 5.2.4 Foreground Band Selector 70 5.2.5 Frequency Detector (FD) 71 5.2.6 Frequency Lock Detector (FLD) 72 5.2.7 Phase Detector (PD) 73 5.2.8 Digital Loop Filter (DLF) 74 5.3 Circuit Implementation 76 5.3.1 Pre-accumulation for PD 76 5.3.2 Digital Control Oscillator (DCO) 76 5.3.3 Time to Digital Converter (TDC) 78 5.3.4 Phase Selector for TDC 80 5.4 The Analyses 81 5.4.1 Frequency Loop 81 5.4.2 Phase Loop 83 5.5 Die Photo, Floor Plan and Pad 84 5.6 Simulation Results 86 5.7 Conclusion and Future Works 87 Bibliography 89 Biography 93 Publications List 95 | |
| dc.language.iso | en | |
| dc.subject | 時脈資料回復電路 | zh_TW |
| dc.subject | 時脈產生器 | zh_TW |
| dc.subject | 延遲鎖相迴路 | zh_TW |
| dc.subject | Clock Generator | en |
| dc.subject | DLL | en |
| dc.subject | CDR | en |
| dc.title | 產生任意寬域延遲之低抖動去偏斜時脈產生器與全數位連續資料速率寬追蹤範圍之時脈資料回復電路 | zh_TW |
| dc.title | A De-skew Clock Generator for Arbitrary Delay and An All-Digital Continuous Rate Wide-Capture Range CDR | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,陳巍仁,林宗賢 | |
| dc.subject.keyword | 時脈產生器,延遲鎖相迴路,時脈資料回復電路, | zh_TW |
| dc.subject.keyword | Clock Generator,DLL,CDR, | en |
| dc.relation.page | 96 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-02-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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