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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Cheng-Dow Su | en |
dc.contributor.author | 蘇承道 | zh_TW |
dc.date.accessioned | 2021-06-15T06:51:17Z | - |
dc.date.available | 2012-02-20 | |
dc.date.copyright | 2011-02-20 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-02-15 | |
dc.identifier.citation | [1] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II., vol. 50, no. 11, pp. 815–828, Nov. 2003.
[2] R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. [3] J. Lin, B. Haroun, T. Foo, J.-S.Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, and J. Kirkpatric, “A PVT tolerant 0.18 MHz to 600MHz self-calibrated digital PLL in 90 nm CMOS process,” in Proc .IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2004,pp. 488–541. [4] N. D. Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nmCMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1482–1490,Jul. 2005. [5] “Spread spectrum timing for hard disk drive applications,” http://www.intel.com, Nov. 2000. [6] M. T. LoBue, “Surveying today’s most popular storage interfaces,” Computer, vol. 35, issue 12, pp. 48-55, Dec. 2002. [7] H. Black, “Modulation Theory,” D. Van Nostrand Company, Inc., Princeton, NJ, 1953. [8] Floyd M. Gardner, “Phase lock Techniques,” JOHN WILEY & SONS, INC., 2005 [9] V. Kratyuk, P. Kurmar, U.K. Moon, and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked –Loop Analogy,” IEEE Trans. Circuits Syst. II. , vol. 54, no. 3, March 2007. [10] C.-M. Hsu, “Techniques for high-performance digital frequency synthesis and phase control,” PhD Thesis, Massachusetts Institute of Technology, Sep. 2008. [11] V. Kratyuk, “Digital phase-locked loops for multi-GHz clock generation,” PhD Thesis, Oregon State University, Dec. 2006. [12] R. B Staszewski, P.T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS,” JOHN WILEY & SONS, INC., 2006. [13] C.-M. Hsu, M.Z. Straayer, M.H. Perrott, 'A Low-Noise, Wide-BW 3.6GHz Digital Delta-Sigma Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,' ISSCC 2008 Dig. Tech. Papers, Feb. 2008, pp. 340-617. [14] M.H. Perrott, “Tutorial on Digital Phase-Locked Loops,” CICC 2009, San Jose, CA, Sept. 13, 2009. [15] K. Hardin, J. T. Fessler, D.R. Bush. “Spread Spectrum clock generation for the reduction of radiated emissions,” in Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, pp.227-231. [16] M. Sugawara, T. Ishibashi, K. Ogasawara, M. Aoyama, M. Zwerg, S. Glowinski, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma, “1.5 Gbps, 5150 ppm spread spectrum Serdes PHY with a 0.3mW, 1.5 G/ps level detector for Serial ATA,” in Symp. VLSI Circuit Dig. Tech. Papers, pp.60-63, June 2002. [17] M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, T. Ishibashi, S. Shimoyama, K. yamaguchi, T. Yanagita, T. Noma, “3 Gbps, 5000ppm spread spectrum Serdes PHY with frequency tracking phase interpolators for Serial ATA,” in Symp. VLSI Circuits, pp.107-110, June 2003. [18] J.Y. Michel and C. Neron, “A frequency modulated PLL for EMI reduction in embedded application,” IEEE ASIC/SOC, vol.12, pp.362-365, Sept. 1999. [19] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-spectrum clock generator for Serial ATA using fractional PLL controlled by modulator with level shifter,” IEEE International Solid-State Conference, pp.160-161, Feb. 2005. [20] H.R. Lee, O. Kim, G. Ahn, and D. K. Jeong, “A low jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18um COMS,” IEEE International Solid-State Circuit Conference, pp.162-163, Feb. 2005. [21] R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A First Multi-gigahertz Digitally Controlled Oscillator for Wireless Application,” in IEEE Transactions on Microwave Theory and Techniques, Vol. 51, pp. 2154-2164, Nov. 2003. [22] H. H. Chang, P.-Y. Wang, J.-H. Conan Zhan, B.-Y. Hsieh, “A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE,” IEEE International Solid-State Circuit Conference Dig. Tech. Papers, pp. 200-201, 2008. [23] S. Y. Lin and S. I. Liu, “A 1.5GHz All-Digital Spread-Spectrum Clock Generator,” in Journal of Solid-State Circuits, VOL. 44, pp. 3111-3119, Nov. 2009. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48285 | - |
dc.description.abstract | 隨著電路技術進步,先進製程有越來越適合數位電路設計的優點。為了要跟上市場需求,小晶片面積與低電源供應器電壓已成為現今的一種趨勢。而在更換製程時,數位電路也有容易重新設計的特性。
全數位式鎖相迴路可以將類比的電荷幫浦與迴路濾波器以數位式的電路來取代,是對於積體電路來說的一大好處。 時脈展頻產生器應用於許多系統中,時脈展頻產生器可以將處生的時脈經由展頻功能,將主要的頻率能量分散,降低其每單位頻寬的輻射功率。 本論文為應用於時脈展頻器之全數位式鎖相迴路。在此使用了兩段式的三角積分調變器去增加使用於展頻功能上調變器的解析度。最後,此晶片是提請台積電的90奈米製程製作。 | zh_TW |
dc.description.abstract | Recent advances in integrated circuit (IC) technology make fabrication processes very suitable for digital design. In order to satisfy the market requirement, small area and low voltage designs are mandated nowadays. It is easy to redesign with process changes for digital designs.
The all-digital phase-locked loop (ADPLL), one of the most recent and significant advancements in the integrated circuits, offers the remarkable advantage of replacing the charge pump and the loop filter with digital loop filter. The spread spectrum clock generator (SSCG) can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth. In this thesis, an all-digital phase-locked loop application for SSCG is implemented in this paper. We use two-stage delta-sigma modulator to improve the resolution of DSM in spread-spectrum clock function. Finally, the experimental ship is fabricated in a TSMC 90nm CMOS process. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T06:51:17Z (GMT). No. of bitstreams: 1 ntu-100-R96943148-1.pdf: 3999718 bytes, checksum: 46d052da06534e5e7ca9a83eba19d9a2 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 誌謝 i
摘要 iii Abstract iv Contents v List of Figures ix List of Tables xi Chapter 1 1 1.1 Introduction 1 1.2 Thesis Organization 2 Chapter 2 5 2.1 Introduction 5 2.2 Spread Spectrum Fundamentals 6 2.2.1 Modulation profiles 6 2.2.2 Spread Spectrum Modes 8 2.2.3 Spread Spectrum Methods [7] 10 Chapter 3 13 3.1 Basic Concept 13 3.2 Model of an APLL [9] 16 3.2.1 Linear Model for a P2D 16 3.2.2 Linear Model for a DLF 18 3.2.3 Linear Model for a DCO and divider 22 3.3 Determine the parameters of an APLL 23 3.3.1 Design Parameters Calculation for 1st Order DLF 24 3.3.2 Design Parameters Calculation for 2st Order DLF 27 3.3.3 Noise Transfer Function [14] 29 Chapter 4 33 4.1 Introduction 33 4.2 System and Circuit Implement for ADPLL 34 4.2.1 Overview for ADPLL 34 4.2.2 Phase / Frequency Detector and Time to Digital Converter 35 4.2.3 Digital Loop Filter 41 4.2.4 Digital-Controlled Oscillator [21] 44 4.2.5 Programmable Divider 51 4.2.6 TSPC Divider 52 4.3 System and Circuit Implement for SSCG 53 4.3.1 Two-Stage Delta-Sigma Modulation for SSCG 54 4.3.2 Calibration of the Varactor 56 4.3.3 Compensation of Two-Stage DSM 59 4.4 System Simulation 62 4.4.1 Simulate and Verify System 62 4.5 Summary 68 Chapter 5 71 5.1 Introduction 71 5.2 Layout and Floor plan 71 5.3 Test Strategy 73 5.3.1 Test Setup 73 5.3.2 FPGA Setup 74 5.3.3 Print Circuit Board Design 74 5.4 Chip Die Photo 75 5.5 Experimental Results 76 Chapter 6 81 Bibliography 83 Biography 88 | |
dc.language.iso | en | |
dc.title | 應用於展頻之全數位式鎖相迴路 | zh_TW |
dc.title | An All Digital PLL for Spread Spectrum Clock Generator | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳巍仁(Wei-Zen Chen),劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 全數位式鎖相迴路,時脈展頻產生器, | zh_TW |
dc.subject.keyword | All-digital phase-locked loop (ADPLL),spread spectrum clock generator (SSCG), | en |
dc.relation.page | 88 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-02-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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