請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47470完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Hung-Yen Tai | en |
| dc.contributor.author | 戴宏彥 | zh_TW |
| dc.date.accessioned | 2021-06-15T06:01:22Z | - |
| dc.date.available | 2013-08-18 | |
| dc.date.copyright | 2010-08-18 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-16 | |
| dc.identifier.citation | Reference
[1] B. P. Ginsburg, and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 4, pp. 739–747, Apr. 2007. [2] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, C.-K. Wang “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 149-152, Nov. 2009. [3] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/conversion-step 10b 1MSs charge redistributed ADC,” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 244-245, Feb.2008. [4] J. L. McCreary, and P. R. Gray, “ All-MOS charge redistribution analog-to-digital conversion techniques-Part I, ” IEEE Journal of Solid-State Circuits (JSSC), vol. SC-10, pp. 371-379, Dec. 1975. [5] S.-W. Michael Chen, and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2669–2680, Dec. 2006. [6] A. Agnes, E. Bonizzoni, F. Maloberti “Design of an ultra-low power SA-ADC with medium/high resolution and speed,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, 2008. [7] H.-W. Chen, Y.-H Liu, Y.-H. Lin, and H.-S. Chen “A 3mW 12b sub-range SAR ADC,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 153-156, Nov. 2009. [8] Y. Chen, S. Tsukamoto, and T. Kuroda “A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 145-148, Nov. 2009. [9] G.-Y. Huang, C.-C. Liu, Y.-Z. Lin, S.-J. Chang, “A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 157-160, Nov. 2009. [10] Y. Chen, S. Tsukamoto, and T. Kuroda “Split capacitor DAC mismatch calibration in successive approximation ADC,” IEEE Custom Integrated Circuits Conference (CICC), pp. 279-282, Sep. 2009. [11] Y. Chen, S. Tsukamoto, and T. Kuroda “A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 145-148, Nov. 2009. [12] S. Gambini, J. Rabaey, “Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 11, pp. 2348-2356, Nov. 2007. [13] G. Van der Plas, B. Verbruggen, “A 150 MS/s 133 uW 7 bit ADC in 90 nm Digital CMOS” IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 12, pp. 2631-2640, Dec. 2008. [14] F. Kuttner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 136-137, 2002. [15] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “ A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, ” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 731-740, Apr. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47470 | - |
| dc.description.abstract | 一個10位元解析度每秒80萬次取樣的循序漸近式類比至數位轉換器(SAR ADC)實現在TSMC的90nm製程上，此 SAR ADC 可以在低電壓下操作的很好。在使用分離式電容切換技巧上面，功率消耗僅為2.88微瓦，換算成FoM為10.2fJ/c.s.。
因為 SAR ADC 的功率消耗約為0.5*C*V2*f，所以可以藉由減少電晶體本身的電容與降低工作電壓來節省所需的功率消耗。此晶片使用先進製程且供應電壓為0.5V，並使用了電荷升壓技巧讓取樣開關能完全的開啟或關閉，加上為了讓比較器的輸入差動對能使用NMOS，採用了電壓位準平移的方式來達成此目的。此晶片在量測中得到SFDR為66.19dB，SNDR為52.72dB且換算成ENOB為8.47bit。整個晶片所佔的面積為0.49mm2，而主動電路只有0.038mm2。 | zh_TW |
| dc.description.abstract | A 10-bit 800KS/s SAR ADC (Successive Approximation Register Analog to Digital Converter) is demonstrated in a standard TSMC 90nm process. This SAR ADC can operate well in low supply voltage. By using split-capacitor technique, its power consumption is only 2.88uW. The FoM (Power / 2ENOB / Fs) of this chip is 10.2fJ / conversion-step.
Since the power of SAR ADC approximates to 0.5*C*V2*f, it can save power by reducing the MOS capacitor and lowering the supply voltage. This chip is implemented in advanced process and its supply voltage is 0.5V. In such a low voltage, it uses a charge pump to fully turn on or turn off the sampling switch. For the purpose of using NMOS input pair comparator, the level-shift method is adopted. The measurement results show that the SFDR is 66.19dB, the SNDR is 52.72dB, and the ENOB is 8.47-bit. The chip size occupies 0.49 mm2, and the active area is only 0.038 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T06:01:22Z (GMT). No. of bitstreams: 1 ntu-99-R97943132-1.pdf: 3098983 bytes, checksum: bccba41364ecd8e9f844d102006a0019 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Table of Contents
致謝 I 摘要 II Abstract III Table of Contents IV List of Figures VII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Performance metrics of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Static performance (DNL and INL) 3 2.2.2 Signal-to-Noise Ratio (SNR) 5 2.2.3 Total Harmonic Distortion (THD) 6 2.2.4 Spurious-Free Dynamic Range (SFDR) 6 2.2.5 Signal-to-Noise and Distortion Ratio (SNDR) 6 2.2.6 Effective Number of Bits (ENOB) 7 2.2.7 Figure of Merit (FoM) 7 Chapter 3 Architecture of Analog-to-Digital Converters 8 3.1 Architecture of Analog-to-Digital Converters 8 3.2 SAR ADC 8 3.3 Flash ADC 10 3.4 Two-Step ADC 11 3.5 Folding ADC 12 3.6 Pipelined ADC 13 3.7 Summary 14 Chapter 4 Energy-Saving Concept 15 4.1 Introduction 15 4.2 Energy-Saving Concept 16 4.2.1 Low Voltage 16 4.2.2 Asynchronous 17 4.2.3 Capacitor Array 19 4.2.4 Capacitor Switching Method 21 Chapter 5 Circuit Implementation and Simulation Results 24 5.1 Introduction 24 5.2 Implementation and Simulation 24 5.2.1 Asynchronous 24 5.2.2 Charge Pump 31 5.2.3 Capacitor Array 34 5.2.4 Comparator 40 5.3 Summary 42 Chapter 6 Chip Setup and Measurement Results 46 6.1 Introduction 46 6.2 Chip Setup 46 6.2.1 Layout 46 6.2.2 PCB and Instruments 48 6.2.3 Bandpass Filter 50 6.3 Measurement Results 51 6.3.1 Static Performance 51 6.3.2 Dynamic Performance 52 6.3.3 Power 55 6.4 Summary 55 Chapter 7 Conclusions 56 Reference 59 | |
| dc.language.iso | en | |
| dc.subject | 循序漸進 | zh_TW |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 低電壓 | zh_TW |
| dc.subject | SAR | en |
| dc.subject | ADC | en |
| dc.subject | Low Power | en |
| dc.subject | Low Voltage | en |
| dc.title | 一個超低功率消耗的類比數位轉換器 | zh_TW |
| dc.title | An Ultra-low Power Analog to Digital Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋,蔡宗亨,洪浩喬 | |
| dc.subject.keyword | 循序漸進,類比至數位轉換器,低功率,低電壓, | zh_TW |
| dc.subject.keyword | SAR,ADC,Low Power,Low Voltage, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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