請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47415完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Yen-Chuan Huang | en |
| dc.contributor.author | 黃彥筌 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:58:48Z | - |
| dc.date.available | 2011-08-18 | |
| dc.date.copyright | 2010-08-18 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-16 | |
| dc.identifier.citation | [1] H. van der Ploeg and B. Nauta, Calibration Techniques in Nyquist A/D Converters, Springer, Dordrecht, 2006.
[2] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, New York, 1995. [3] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997. [4] F. Maloberti, Data Converters, Springer, Dordrecht, 2007. [5] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communi -cations, Kluwer Academic Publisher, Boston, 2000. [6] B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b Cyclic RSD A/D Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 957-965, Jul. 1992. [7] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [8] J. Li, X. Zeng, L. Xie, J. Chen, J. Zhang, and Y. Guo, “A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications,” IEEE J. of Solid-State Circuits, vol. 43, pp. 321-329, Feb. 2008. [9] I. Ahmed and D. A. Johns, “A High Bandwidth Power Scalable Sub-Sampling 10-bit Pipelined ADC with Embedded Sample and Hold,” IEEE J. of Solid-State Circuits, vol. 43, pp. 1638-1647, Jul. 2008. [10] J. Craninckx and G. van der Plas, “A 65fJ/Conversion-Step 0-to-50MS/s 0-to -0.7mW 9b Charging Sharing SAR ADC in 90nm Digital CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247. [11] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx, “An 820W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 238-239. [12] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique,” IEEE J. of Solid-State Circuits, vol. sc-19, pp. 828-836, Dec. 1984. [13] O. E. Erdogan, P. J. Hurst, and S. H. Lewis, “A 12-b Digital-Background -Calibrated Algorithmic ADC with -90-dB THD,” IEEE J. of Solid-State Circuits, vol. 34, pp. 1812-1820, Dec. 1999. [14] D.-Y. Chang, G.-C. Ahn, and U.-K. Moon, “Sub-1-V Design Techniques for High- Linearity Multistage/Pipelined Analog-to-Digital Converters,” IEEE Trans. Circuits and Syst. I, vol. 52, pp. 1-12, Jan. 2005. [15] S. Kawahito, J.-H. Park, K. Isobe, S. Shafie, T. Iida, and T. Mizota, “A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits,” in ISSCC. Dig. Tech. Papers, Feb. 2008, pp. 56-57. [16] E. B. Blecker, T. M. McDonald, O. E. Erdogan, P. J. Hurst, and S. H. Lewis, “Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a Simplified Queue,” IEEE J. of Solid-State Circuits, vol. 38, pp. 1059- 1062, Jun. 2003. [17] B. K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, vol. 18, pp. 629-633, Dec. 1983. [18] D. B. Ribner and M. A. Copeland, “Design techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-Mode Input Range,” IEEE J. of Solid-State Circuits, vol. 19, pp. 919-925, Dec. 1984. [19] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2001. [20] D. W. Cline and P. R. Gray, “Noise, Speed, and Power Trade-offs in Pipelined Analog to digital Converters,” Ph.D. dissertation, Univ. of California, Berkeley, 1995 [21] K. Honda, Z. Liu, M. Furuta, and S. Kawahito, “A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique,” in Symp. VLSI Circuits Dig. Papers, Jun. 2007, pp. 196-197. [22] T. B. Cho and P. R. Gray, “A 10 b, 20Msample/s 35mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995. [23] H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15-b 40-MS/s CMOS Pipelined Analog -to-Digital Converter with Digital Background Calibration,” IEEE J. of Solid-State Circuits, vol. 40, pp. 1047-1056, May 2005. [24] M.-J. Kim, H.-S. Yoon, Y.-J. Lee, and S.-H. Lee, “An 11b 70 MHz 1.2 mm2 49 mW 0.18 um CMOS ADC with On-Chip Current/Voltage References,” in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2002, pp. 463-466. [25] Y.-D Jeon, S.-C. Lee, K.-D. Kim, J.-K. Kwon, and J. Kim “A 4.7-mW 0.32mm2 10b 30MS/s Pipelined ADC without a Front-End S/H in 90nm CMOS,” in ISSCC. Dig. Tech. Papers, Feb. 2007, pp. 456-457. [26] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC using Dynamic Residue Amplification,” in Symp. VLSI Circuits Dig. Papers, Jun. 2008, pp. 216-217. [27] L. Brooks and H.-S. Lee, “A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC,” IEEE J. of Solid-State Circuits, vol. 42, pp. 2677-2687, Dec. 2007. [28] L. Brooks and H.-S. Lee, “A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 166-167. [29] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. of Solid-State Circuits, vol. 44, pp. 1057-1066, Apr. 2009. [30] I. Ahmed, J. Mulder, and D. A. Johns, “A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18um CMOS Using Capacitive Charge-Pumps,” in ISSCC. Dig. Tech. Papers, Feb. 2009, pp. 164-165. [31] M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, “A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS,” in ISSCC. Dig. Tech. Papers, Feb. 2008, pp. 250-251. [32] G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, and R. Verlinden, “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC with 0.5-pJ/Conversion-step,” in ISSCC. Dig. Tech. Papers, Feb. 2006, pp. 214-215. [33] M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto, “A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing,” in ISSCC. Dig. Tech. Papers, Feb. 2007, pp. 452-453. [34] K. Honda, M. Furuta, and S. Kawahito, “A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques,” IEEE J. of Solid-State Circuits, vol. 42, pp. 757-765, Apr. 2007. [35] S.-T. Ryu, B.-S. Song, and K. Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse,” IEEE J. of Solid-State Circuits, vol. 42, pp. 475-485, Mar. 2007. [36] B.-G. Lee and R. M. Tsang, “A 10-bit 50 MS/s Pipelined ADC With Capacitor Sharing and Variable-gm Opamp,” IEEE J. of Solid-State Circuits, vol. 44, pp. 883-890, Mar. 2009. [37] M. G. Kim, P. K. Hanumolu, and U.-K. Moon, “A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC with Improved Clocking Scheme,” IEEE J. of Solid-State Circuits, vol. 44, pp. 2348-2355, Sep. 2009. [38] J. Shen and P. R. Kinget, “A 0.5-V 8-bit 10-MS/s Pipelined ADC in 90-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 43, pp. 787-795, Apr. 2008. [39] S.-C. Lee, K.-D. Kim, J.-K. Kwon, J. Kim, and S.-H. Lee, “A 10-bit 400-MS/s 160-mW 0.13-μm CMOS Dual Channel Pipeline ADC without Channel Mismatch Calibration,” IEEE J. of Solid-State Circuits, vol. 41, pp. 1596-1605, Jul. 2006. [40] Y.-S. Shu, M. J. Kyung, W.-M. Lee, B. S. Song, and B. Pain, “A 10~15-bit 60-MS/s Floating-Point ADC with Digital Gain and Offset Calibration,” IEEE J. of Solid-State Circuits, vol. 44, pp. 2356-2365, Sep. 2009. [41] H. C. Yang and D. J. Allstot, “Considerations for Fast Settling Operational Amplifiers,” IEEE Trans. Circuits Syst. I, vol. 37, pp. 326-334, Mar. 1990. [42] P. Y. Wu, V. S.-L. Cheung, and H.-C. Luong, “A 1-V 100-MS/s 8-bit Switched- Opamp Pipelined ADC Using Loading-Free Architecture,” IEEE J. of Solid-State Circuits, vol. 432, pp. 730-738, Apr. 2007. [43] N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu, and U.-K. Moon, “A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback,” IEEE J. of Solid-State Circuits, vol. 44, pp. 2392-2401, Sep. 2009. [44] W.-T. Tu and T.-H. Kang, “A 1.2V 30mW 8b 800MS/s Time-Interleaved ADC in 60nm CMOS,” in Symp. VLSI Circuits Dig. Papers, Jun. 2008, pp. 72-73. [45] C.-C. Hsu, C.-C. Huang, Y.-H. Lin, C.-C. Lee, Z. Soe, T. Aytur, and R.-H. Yan, “A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS,” in Symp. VLSI Circuits Dig. Papers, Jun. 2007, pp. 66-67. [46] Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS Pipelined ADC With Over 100-dB SFDR,” IEEE J. of Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004. [47] E. Alpman, H. Lakdawala, L. R. Carley, and K. Soumyanath, “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS,” in ISSCC. Dig. Tech. Papers, Feb. 2009, pp. 76-77. [48] W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization,” in ISSCC. Dig. Tech. Papers, Feb. 2009, pp. 82-83. [49] C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.-C. Huang, Y.-H. Lin, C.-C. Lee, and B. Razavi, “An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration,” in ISSCC. Dig. Tech. Papers, Feb. 2007, pp. 464-465. [50] S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10b, 175mW Time-Interleaved AD Converter in 0.13μm CMOS,” IEEE J. of Solid- State Circuits, vol. 43, pp. 778-786, Apr. 2008. [51] D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” IEEE J. of Solid- State Circuits, vol. 43, pp. 1904-1911, Dec. 1998. [52] S. M. Jamal, D. Fu, C.-J. Chang, P. J. Hurst, and S. H. Lewis, “A 10-b 120- Msample/s Time-Interleaved Analog-to-Digital Converter with Digital Back- ground Calibration,” IEEE J. of Solid- State Circuits, vol. 37, pp. 1618-1627, Dec. 2002. [53] M. Gustavsson and N. Tan, “A Global Passive Sampling Technique for High- Speed Switched-Capacitor Time-Interleaved ADCs,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 821-831, Sep. 2000. [54] S. K. Gupta, M. A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture,” IEEE J. of Solid- State Circuits, vol. 41, pp. 2650-2657, Dec. 2006. [55] A. Verma and B. Razavi, “A 10-Bit 500-MS/s 55-mW CMOS ADC,” IEEE J. of Solid- State Circuits, vol. 44, pp. 3039-3050, Nov. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47415 | - |
| dc.description.abstract | 類比數位轉換器是連接真實世界與離散運算領域的關鍵元件，此篇論文主要介紹迴圈式與管線式類比數位轉換器之設計，以類比的方式，達到小面積、低功率消耗等設計目標。
在本篇論文中，首先提出並分析一個以部分正回授迴圈為架構之乘二電路，其次介紹應用此電路之迴圈式類比數位轉換器的設計與工作原理。由於此轉換器之殘值計算與取樣相位的結合，故只需四個時脈週期，即可完成九位元的轉換，與通常需要十個時脈週期的傳統架構相較，轉換延遲大幅縮短。提出之架構已於九十奈米製程中實現；電路核心所佔的晶片面積只有0.02平方毫米，是目前相似解析度的類比數位轉換器裡，晶片面積最小的設計。實驗量測結果顯示，當轉換頻率為五千萬赫茲時，信噪失真比(SNDR)約為50.5分貝，核心電路功率消耗則約為6.9毫瓦。 接著是介紹一個時間分享的技巧來降低管線式類比數位轉換器整體的功率消耗，改善傳統運算放大器分享架構之功率效益。所設計之類比數位轉換器只需要一個運算放大器就可以完成十位元的轉換。提出之架構也於九十奈米製程中實現；電路核心所需要的晶片面積為0.058平方毫米。實驗量測結果顯示，當轉換頻率為一億赫茲時，信噪失真比(SNDR)約為55.0分貝，而核心功率消耗約為4.5毫瓦。 最後一個設計則是並聯前述之十位元轉換器，將轉換頻率進一步提升，達到四億赫茲。實驗量測結果顯示，信噪失真比(SNDR)約為53.0分貝，而整體功率消耗約為36毫瓦。 | zh_TW |
| dc.description.abstract | Analog-to-digital (A/D) converters which provide the link between the analog world and digital domain represent important building blocks in many systems. In this dissertation, three ADCs are presented to achieve small-area and low-power design objectives with analog approaches.
First, a 9-bit cyclic ADC employs a novel multiply-by-two circuit for enhancing the speed of residue evaluation is presented. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform a 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a core power consumption of 6.9 mW from a 1.0-V supply. Then, a 10-bit pipelined ADC employs both opamp and time sharing techniques to reduce the power consumption and silicon area is proposed. This ADC needs only one opamp to complete the 10-bit conversion. The prototype design also has been fabricated in 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the core power consumption is 4.5 mW from a 1.0-V supply. The last work was an extension of the second design. The conversion rate is efficiently boosted by four ADCs in parallel. The measured results give an SNDR of 53.0 dB and power consumption of 36 mW at a sampling rate of 400 MHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:58:48Z (GMT). No. of bitstreams: 1 ntu-99-D94943013-1.pdf: 1499537 bytes, checksum: 648da141b910f6313856d91b153ca41e (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 iii Abstract iv Contents v List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converters 5 2.1 Introduction 5 2.2 ADC Performance Metrics 5 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 5 2.2.2 Signal-to-Noise Ratio (SNR) 8 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 9 2.2.4 Effective Number-of-Bits (ENOB) 10 2.2.5 Spurious-Free Dynamic Range (SFDR) 10 2.2.6 Figure of Merit (FoM) 11 2.3 Architectures of Analog-to-Digital Converters 11 2.3.1 Flash Architecture 12 2.3.2 Two-Step and Sub-Ranging Architecture 13 2.3.3 Pipelined Architecture 15 2.3.4 Cyclic (Algorithmic) Architecture 16 2.4 Digital Error Correction 17 2.4.1 Out of Range Error 18 2.4.2 Over Range Error Correction 18 2.4.3 1.5-Bit Pipelined Stage 22 2.5 Summary 26 Chapter 3 A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS 27 3.1 Introduction 27 3.2 Conventional Cyclic ADC Architecture Review 28 3.3 Proposed Architecture 30 3.3.1 Settling Time of the Proposed Cyclic Stage 33 3.3.2 Current-Switching Track-and-Hold 37 3.3.3 Timing for the Cyclic ADC 41 3.3.4 Track-and-Evaluation Characteristic 42 3.4 Experimental Results 44 3.5 Summary 51 Chapter 4 A 10-bit 100-MS/s Pipelined ADC with a Time-Sharing Technique 53 4.1 Introduction 53 4.2 Time-Sharing Technique 56 4.3 Circuit Implementation 60 4.3.1 Input Sampling Network 60 4.3.2 Opamp Design 62 4.3.3 Capacitor Sharing Technique 66 4.4 Experimental Results 71 4.5 Summary 78 Chapter 5 A 10-bit 400-MS/s Interleaved Pipelined ADC 79 5.1 Interleaved Architecture 79 5.1.1 Offset Errors 80 5.1.2 Gain Mismatch 81 5.1.3 Phase Skew 82 5.2 Circuit Implementation 84 5.2.1 Track-and-Hold (T/H) Buffer 85 5.2.2 Gain/Offset Mismatch Correction 87 5.3 Simulation Results 89 5.4 Experimental Results 91 5.5 Summary 94 Chapter 6 Conclusions 97 Bibliography 99 Publication List 107 | |
| dc.language.iso | en | |
| dc.title | 奈米級互補式金氧半製程之管線式類比數位轉換器設計 | zh_TW |
| dc.title | The Design of Nanometer CMOS Pipelined A/D Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 郭泰豪,吳介琮,鄭國興,陳巍仁,黃柏鈞,劉深淵 | |
| dc.subject.keyword | 類比數位轉換,迴圈式類比數位轉換器,管線式類比數位轉換器,運算放大器分享技巧,時間分享技巧, | zh_TW |
| dc.subject.keyword | analog-to-digital conversion,cyclic ADC,pipelined ADC,opamp-sharing technique,time-sharing technique, | en |
| dc.relation.page | 107 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-99-1.pdf 目前未授權公開取用 | 1.46 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。