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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47346完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Hong-Lin Chen | en |
| dc.contributor.author | 陳泓霖 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:55:54Z | - |
| dc.date.available | 2013-08-18 | |
| dc.date.copyright | 2010-08-18 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-17 | |
| dc.identifier.citation | [1] B. Nauta and A. G. W. Venes, “A 70MSample/s 110mW 8b CMOS Folding Interpolating A/D Converter, ” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1995, pp. 276-277.
[2] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, “ A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 252-253, Feb. 2008. [3] K. Kattmann and J. Barrow, “A technique for reducing differential non-linearity errors in flash A/D converters,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1991, pp. 170–171. [4] S. Park, Y. Palaskas, and M. P. Flynn, “A 4 GS/s 4b Flash ADC in 0.18 μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1865–1872, Sep. 2007. [5] G. Van der Plas, S. Decoutere, S. Donnay, “A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 566-567, Feb. 2006. [6] Akira Matsuzawa et al. , “A 6bit, 7mW,250fJ, 700MS/s Subranging ADC,” in Proc. IEEE Asian Solid-State Circuits Conference, pp. 141-144, Nov. 2009. [7] G. Van der Plas, B. Verbruggen, “A 150 MS/s 133 μW 7 bit ADC in 90 nm Digital CMOS,” IEEE J. Solid State Circuits, vol. 43, no. 12, pp.2631-2640, Dec.2008. [8] K. Bult and A. Buchwald, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1 mm^2”, IEEE Journal of Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997. [9] P.M. Figueiredo, J.C. Vital, “Averaging technique in flash analog-to-digital converters,” IEEE Trans. Circuits Syst.-I: Fundamental Theory and Applications, vol. 51, no. 2, pp. 233-253, Feb 2004. [10] M. v. Elzakker, E. V. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B.Nauta “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge Redistribution ADC,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 244-245, Feb. 2008. [11] Y.-C. Lie n and J. Lee, “A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology,”in IEEE Asian Solid-State Circuits Conference, pp.45-48, 3-5 Nov. 2008. [12] K. Deguchi et al., “A 6-bit 3.5GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 43 No.10 pp. 2303-2310 Oct. 2008. [13] Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, and Hsin-Shu Chen, “A 1-GS/s 6-bit Two-Channel Two-Step ADC in 0.13-μm CMOS' in IEEE Journal of Solid-State Circuits, pp. 3051-3059, Nov. 2009. [14] Michio Yotsuyanagi et al., “A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture,” IEEE J. Solid-State Circuits, vol. 45 pp. 707-718 Apr. 2010 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47346 | - |
| dc.description.abstract | 60G 寬頻無線通訊系統需要一個快速的 ADC(4-7 bits)。Flash ADC 被用在許多高速產品像收音機、光通訊、光學讀取頭和超寬頻無線接收器。本論文提出一個應用於高速的六位元動態折疊式快閃式類比數位轉換器設計。利用折疊把傳統快閃式類比數位轉換器所需的比較器數目大大減少，因此可以降低功率，且只消耗動態功率又不需校正的省電類比數位轉換器。並為了消除製程變異造成的誤差，我們採用電阻平均技術。
本晶片使用台積電 90-nm CMOS 製程製作，根據量測結果，本晶片在1GHz的轉換頻率下的DNL和INL分別為-0.6/+0.8LSB和-0.6/+0.8LSB，在輸入頻率為9.99MHz且工作在80MHz的轉換頻率下時，量測到的SNDR和SFDR分別為33.74dB和49.93dB，當輸入頻率為466.544MHz且工作在1GHz的轉換頻率時，其SNDR和SFDR分別為30.07dB和37.19dB，操作在1.2伏特電壓時功率消耗為25mW，全部的晶片面積大小為0.46mm^2，然而主動電路所占的面積只有0.07mm^2。 | zh_TW |
| dc.description.abstract | Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution (4-7 bits). Flash ADC offers the highest sampling rate, which is adapted in these high speed applications such as radio astronomy, optical communication, magnetic and optical read channels, and ultra-wideband wireless receivers. In this paper, we propose a high-speed Dynamic Folding Flash A/D Converter. Use of folding the traditional flash analog to digital converter comparator required substantially reduce the number, it can reduce the power, dynamic power consumption and does not need calibration type analog to digital converter. To alleviate random offset caused by process variation, resistive averaging technique is adopted.
This ADC is demonstrated in a standard 90-nm CMOS process. According to the measurement results, the prototype ADC exhibits a DNL of -0.6/+0.8LSB and an INL of -0.6/+0.8LSB at the sampling rate of 1GS/s. With 9.99MHz input frequency, the SNDR and SFDR achieve 33.74dB and 49.93dB at 80MS/s. The SNDR and SFDR are 30.07dB and 37.19dB at 1GS/s in 466.544MHz input frequency. The power consumption is 25mW at 1.2V supply. The active area is 0.07mm^2and whole chip with pads occupies 0.46mm^2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:55:54Z (GMT). No. of bitstreams: 1 ntu-99-R96943160-1.pdf: 2065701 bytes, checksum: 919b5f42b020591032d23b804cae943c (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Table of Contents
致謝 ................................................... I 摘要 .................................................. II Abstract ............................................. III Table of Contents ..................................... IV List of Tables ......................................... X Chapter 1 .............................................. 1 Introduction ........................................... 1 1.1 Motivation ......................................... 1 1.2 Thesis Organization ................................ 2 Chapter 2 .............................................. 4 Fundamentals of Analog-to-Digital Converters ........... 4 2.1 Introduction ....................................... 4 2.2 Performance Metrics ................................ 4 2.2.1 Offset and Gain Error ............................ 4 2.2.2 Differential and Integral Nonlinearity (DNL, INL). 4 2.2.3 Signal-to-Noise Ratio (SNR) ...................... 6 2.2.4 Total Harmonic Distortion (THD) .................. 7 2.2.5 Spurious-Free Dynamic Range (SFDR) ............... 7 2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) ...... 8 2.2.7 Effective Number of Bits (ENOB) .................. 8 2.2.8 Figure of Merit (FoM) ............................ 9 2.3 Architecture of Analog-to-Digital Converters ....... 9 2.3.1 Flash ADC ........................................ 9 2.3.2 Two-Step ADC .................................... 11 2.3.4 Folding ADC ..................................... 12 2.3.5 Pipelined ADC ................................... 14 2.3.4 Successive-Approximation ADC .................... 15 2.4 Summary ........................................... 17 Chapter 3 ............................................. 18 Proposed architecture ................................. 18 3.1 Introduction ...................................... 18 3.2 Propose ADC Architecture .......................... 19 3.2.1 Timing .......................................... 21 3.2.2 CFs Transfer Function ........................... 23 Chapter 4 ............................................. 25 Circuit Implementation and Simulation Results ......... 25 4.1 CFs ............................................... 25 4.2 CADC and FADCs .................................... 31 4.3 Dynamic averaging network ......................... 32 4.4 Dynamic comparator latch .......................... 38 4.5 Digital error correction .......................... 39 4.6 Clock Generator ................................... 41 4.7 Simulation Results ................................ 43 4.7.1 Charge Folding (CF) Gain ........................ 43 4.7.2 The offset effect of Dynamic Average network .... 44 4.7.3 Simulated Result with Ramp Input ................ 44 4.7.4 DNL and INL Simulation .......................... 45 4.7.5 FFT Simulation .................................. 45 4.8 Summary ........................................... 47 Chapter 5 ............................................. 49 Test Setup and Measurement Results .................... 49 5.1 Introduction ...................................... 49 5.2 Floor Plan and Layout Considerations .............. 49 5.3 Test Setup ........................................ 50 5.4 PCB Design ........................................ 53 5.5 Experiment Results ................................ 57 5.5.1 Static Performance .............................. 60 5.5.2 Dynamic Performance ............................. 61 5.6 Summary ........................................... 64 Chapter 6 ............................................. 67 Conclusions ........................................... 67 Bibliography .......................................... 69 | |
| dc.language.iso | en | |
| dc.subject | 快閃型式 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 平均電阻網路 | zh_TW |
| dc.subject | 摺疊型式 | zh_TW |
| dc.subject | averaging network | en |
| dc.subject | flash | en |
| dc.subject | folding | en |
| dc.subject | Analog-to-digital conversion | en |
| dc.title | 一個操作在高速的六位元動態折疊式快閃類比數位轉換器 | zh_TW |
| dc.title | A high-speed 6b Dynamic Folding Flash A/D Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋,蔡宗亨,洪浩喬 | |
| dc.subject.keyword | 類比數位轉換器,平均電阻網路,摺疊型式,快閃型式, | zh_TW |
| dc.subject.keyword | Analog-to-digital conversion,averaging network,folding,flash, | en |
| dc.relation.page | 71 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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