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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | Yuen-Tai Chang | en |
| dc.contributor.author | 張元泰 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:52:06Z | - |
| dc.date.available | 2015-08-19 | |
| dc.date.copyright | 2010-08-19 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-17 | |
| dc.identifier.citation | [1] M. H. Perrott, T. L. Tewksbury III and C. G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK Modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997
[2] D. Banerjee, PLL performance, simulation, and design, National Semiconductor, Available on: http://webench.national.com/appinfo/wireless/files/deansbook4.pdf [3] Murata, M. Ohhata, M. Togashi, and M. Suzuki, “20 Gb/s GaAsMESFET multiplexer IC using a novel T-type flip-flop circuit,” IEEElectron. Lett., vol. 28, no. 22, pp. 2090–2091, 1992 [4] William B. Wilson, Un-Ku moon, Kadaba R.Lakshmikumar and Liang Dai ,“A CMOS Self-Calibrating Frequency Synthesizer,” IEEE JSSCC, VOL. 35, NO. 10, OCTOBER 2000 [5] Dah-Chung Chang, “Least Squares/Maximum Likelihood Methods for the Decision-Aided GFSK Receiver,” IEEE SIGNAL PROCESSING LETTERS, VOL. 16, NO. 6, JUNE 2009 [6] Taiichi Otsuji, Mikio Yoneyama, Koichi Murata Eiichi Sano, “A Super-Dynamic Flip-Flop Circuit for Broad-Band Applications up to 24 Gb/s Utilizing Production-Level 0.2-um GaAs MESFET's,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 [7] T.P. Kenny, T.A.D. Riley, N.M. Filiol, and M.A.Copeland, “Design and realization of a digital delta-sigma modulator for fractional-N frequency synthesis,” IEEE Trans. On Vehicular Technology, vol.48, no. 2, pp.510-521, Mar. 1999 [8] D. Banerjee, “PLL Performance, Simulation and Design,” 3rd edition., 2003, National Semiconductor [9] S.Y. Liu, Analysis and Design of Phase-Locked Loops, class notes, Grad. Inst. of Electronics Engineering, National Taiwan University, spring 2010 [10] 李昉亭, A Fractional-N Frequency Synthesizer for 315/433/868/915 MHz ISM Bands, Master Thesis, July. 2007 [11] 楊育哲, The Design and Application of CMOS Fully-Integrated PLL-Based Fractional-N Frequency Synthesizers Circuits, PHD Thesis, June. 2007. [12] 彭康峻, “Wideband GFSK-Modulated Frequency Synthesizer Using Two-Point Delta-sigma Modulation,” PHD Thesis, April. 2005 [13] 林聖紘, ”CMOS PLL-Based Frequency Synthesizers for Broadband Wireless Communication System,” Master Thesis, July, 2008 [14] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999. [15] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996. [16] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. [17] S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 31, pp. 1039-1045, Jul. 2000. [18] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” Proc. of IEEE International Symp. on Circuits and Systems, vol. 2, 1999, pp. 545-548. [19] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Communication, vol. 28, pp. 1849-1858, Nov. 1980 [20] F. M. Garner, “Charge-Pump Phase-Locked Loops,” IEEE Trans. on Communications, pp. 1849-1858, Nov. 1980. [21] National Semiconductor, An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLLs, Application Note 1001, Jul. 2001 [22] 王裕翔，”A Frequency Synthesizer and Low-noise Amplifiers for Wireless Communication,” June, 2009 [23] Michael H. Perrot, Mitchell D. Trott, and Charles G. Sodini ,” A Modeling Approach for delta-sigma Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE JSSC, VOL. 37, NO. 8, AUGUST 2002 [24] Michael H. Perrot, “Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits,” IEEE Design & Test Computers, Special DAC Section, pp. 74-83, July-August 2002 [25] Yang Yu-Che, Shih-An Yu, Yu-Hsuan Liu, Tao Wang, and Shey-Shi Lu, “A Quantization Noise Suppression Technique for delta-sigma Fractional-N Frequency Synthesizers,” IEEE JSSC, VOL. 41, NO. 11, NOVEMBER 2006 [26] Dickson T.S. Cheung, John R. Long, R.A. Hadaway, and D.L. Harame “Monolithic Transformers for Silicon RF IC Design,” IEEE BCTM 6.1 [27] C. Patrick Yue, and S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's,” IEEE JSSC, VOL. 33, NO. 5, MAY 1998 [28] J.J. Rael and A.A. Abidi, “Physical Processes of Phase Noise in Differential LC Oscillators,” IEEE CUSTOM INTEGRATED CIRCUITS CONFERNCE [29] D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” proceedins of the IEEE, vol. 54, pp. 329-330, 1966 [30] KaChun Kwok, and Howard C. Luong, “Ultra-Low-Voltage High-Performance CMOS VCOs Using Transformer Feedback,” IEEE JSSC, VOL. 40, NO. 3, MARCH 2005 [31] B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998. [32] Ali Hajimiri and T. H. Lee, ”A general theory of phase noise in electricaloscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, 1998 [33] Razavi. B, et al, “Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS”, IEEE Journal of SolidState Circuits, vol. 30, No. 2, Feb. 1995, pp.101-109. [34] “An Analysis and Performance Evaluation of a Passive Filter DesignTechnique for Charge Pump PLL’s,” National Semiconductor application note,July 2001 [35] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A Modeling Approach for Σ-Δ Fractional-N Frequency Synthesizer Allowing Straightforward Noise Analysis,” IEEE JOURANL of Solid State Circuits, vol. 37, No. 8, Aug. 2002, pp.1028-103 [36] Michael Steer, “Microwave and RF design: A systems approach,” Scitech publishing inc. 2009 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47244 | - |
| dc.description.abstract | 本論文共大分為二個部分，第一個部分為研製一個10/5/2.4 GHz的分數型頻率合成器，第二個部分為研製一個以分數型頻率合成器為架構之2.4GHz高斯頻率鍵移(Gaussian Frequency Shift Keying, GFSK)傳輸機。
論文中第一個部分為一個具有自動頻率校正之適用於10/5/2.4 GHz的多頻段分數型頻率合成器，藉由一鎖相迴路內之壓控振盪器VCO輸出第一個頻段，再經由動態除頻器輸出第二個頻段，最後再透過高速電流模式除頻器輸出第三個頻段以達成應用於10/5/2.4 GHz之通訊系統。 論文中第二個部分為一個以分數型頻率合成器為架構之2.4GHz高斯頻率鍵移傳輸機。此高斯頻率鍵移傳輸機採用8位元之數位三角積分器，高斯濾波器及一閉迴路鎖相迴路作為核心電路。也因採用閉迴路鎖相迴路架構及不需混波器，故此傳輸機系統具有好的相位雜訊、較低的電路復雜度等特性。 關鍵字：鎖相迴路 ，三角積分器，分數型鎖相迴路，頻率合成器，高斯頻率鍵移,傳輸機, 2.4GHz | zh_TW |
| dc.description.abstract | In this thesis, we roughly divide two part, part one is a 10/5/2.4 GHz fractional-N frequency synthesizer with auto frequency calibration, part two is a 2.4GHz GFSK transmitter base on a fractional-N frequency synthesizer.
In part one, a 10/5/2.4 GHz multiband frequency synthesizer with auto frequency calibration (AFC). To achieve the application of 10/5/2.4 GHz communication system, the first band is directly output of VCO then through a super-dynamic divider output is the second band and then through a current mode logic divider output is the third band. In part two, a GFSK transmitter have been designed and realized base on a 2.4GHz frequency synthesizer. this GFSK transmitter using a 8-bit delta-sigma modulator, Gaussian filter and a close loop phase lock loop. It has good phase noise, easy to implement due to the architecture of close loop and no mixer required. Keywords: PLL, delta-sigma modulator, ∆∑fractional-N frequency synthesizer, GFSK, transmitter, 2.4GHz | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:52:06Z (GMT). No. of bitstreams: 1 ntu-99-R97943063-1.pdf: 3490044 bytes, checksum: 5ea681dc3110ebf49fb291df84bec3e3 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Chapter 1 1
1.1 Introduction 1 1.2 Overview of this thesis 1 Chapter 2 3 2.1 Introduction 3 2.2 General considerations 4 2.2.1 Phase Noise 4 2.2.2 Spurs 6 2.3 Building blocks of PLL 8 2.3.2 Phase/Frequency Detector(PFD) and Charge Pump (CP) 12 2.3.3 Loop Filter 16 Chapter 3 19 3.1 Linear model of Integer-N PLLs 19 3.2. Design of a Phase Lock Loop 22 3.2.1 Second-Order PLL 22 3.2.2 Third-Order PLL 24 3.2.3 Fourth-Order PLL 26 3.3 Phase noise analysis 28 Chapter 4 32 4.1 Introduction 32 4.2 Concept of fractional-N 32 4.3 △∑ (delta-sigma) Frequency Synthesizer 35 4.4 Digital Phase Accumulator (DPA) 36 4.5 First order delta-sigma modulator 37 4.6 Second order delta-sigma modulator 39 4.7 Third order delta-sigma modulator 39 Chapter 5 42 5.1 Architecture of the fraction-N delta-sigma frequency synthesizer 42 5.2 Digital circuit in delta-sigma frequency synthesizer 45 5.2.1Architecture of three-wired interface 45 5.2.2 Architecture of MASH 1-1-1 delta-sigma modulator 46 5.2.3Architecture of auto-frequency control (AFC) 47 5.3 VCO 48 5.3.1 LC-VCO 49 5.3.2 Inductor model 49 5.4 Dividers 53 5.4.1 Truly Modular Programmable Divider 54 5.5 Phase Frequency Detector (PFD) 57 5.6 Charge Pump (CP) 59 5.7 Loop Filter 61 5.8 PLL post-simulation 61 5.8 Design flow 64 5.9 Measurement result 66 5.10 Summary 74 Chapter 6 77 6.1 Introduction 77 6.2 Frequency Modulation Schemes 79 6.3 Gaussian Low Pass Filter 81 6.4 Simulation Result 88 6.5 Summary 91 Chapter 7 93 Bibliography 94 | |
| dc.language.iso | en | |
| dc.subject | 2.4GHz | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 三角積分器 | zh_TW |
| dc.subject | 分數型鎖相迴路 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 高斯頻率鍵移 | zh_TW |
| dc.subject | 傳輸機 | zh_TW |
| dc.subject | GFSK | en |
| dc.subject | 2.4GHz | en |
| dc.subject | transmitter | en |
| dc.subject | PLL | en |
| dc.subject | delta-sigma modulator | en |
| dc.subject | fractional-N frequency synthesizer | en |
| dc.title | CMOS鎖相迴路頻率合成器之研究與應用 | zh_TW |
| dc.title | The Design and Application of CMOS PLL-Based Frequency Synthesizers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,孟慶宗,邱弘緯,陳筱青 | |
| dc.subject.keyword | 鎖相迴路,三角積分器,分數型鎖相迴路,頻率合成器,高斯頻率鍵移,傳輸機,2.4GHz, | zh_TW |
| dc.subject.keyword | PLL,delta-sigma modulator,∆,∑,fractional-N frequency synthesizer,GFSK,transmitter,2.4GHz, | en |
| dc.relation.page | 97 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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