強健且低成本類比數位轉換器輸出碼計數器之實現

Abstract

本論文中提出了一個強健且低成本之ADC字碼計數技術，利用線性斜坡信號當作ADC測試激勵源，可正確地記錄ADC各輸出字碼及其計數次數。技術中使用一個中心字碼追蹤引擎於字碼計數器中，並配合所提出之字碼追蹤演算法，可強健地執行ADC字碼計數功能，有效掌握因隨機雜訊所引起之字碼跳動現象、缺碼現象和非單調性現象。此外，所需測試時間及硬體資源都達到目前已知最好的水準，為過去技術所不能。 該技術在文中主要分為兩個版本討論：基本型及完整型字碼計數版本。基本型版本可容忍雜訊所引起之ADC輸出字碼之跳動現象。而完整型字碼計數版本則不僅可解決上述之字碼跳動現象，對於ADC輸出字碼之缺碼及非單調性現象亦能確實有效掌握、正確計數。 軟體模擬方面，基本型與完整型字碼計數技術利用MATLAB設計規格並模擬其功能行為；隨後，依兩版本能力的不同分別產生各1,000個隨機干擾之ADC輸出序列，以驗證所提出字碼計數技術之正確性其及性能限制。 硬體實現方面，兩版本字碼計數技術使用Verilog硬體描述語言開發其硬體電路，確認電路模擬結果與軟體模擬結果一致；最後，將完整型字碼計數版本經cell-based設計流程，利用TSMC 0.18um Mixed signal (1P6M) CMOS製程技術，實現成為一顆完整型字碼計數器之巨集模塊(macro block)，以便日後整合應用於單晶片ADC 自我測試或自我校正技術中。

This thesis presents a robust, low-cost ADC code hit counting technique to record the number of times each ADC output code word appears with respect to the linear ramp input stimulus. Using a smart center code tracking engine together with the code tracking algorithm, the proposed code hit counter performs robustly against the code transition noise, missing code segments, and non-monotonicity. Furthermore, the required hardware and test time is at the same level as the known best results. The robust code hit counting technique has two versions: the basic and complete versions. The basic version aims to tolerate the code transition noise while the complete version also handles missing code segments and non-monotonicity. To verify the code hit counting technique, behavior simulations of both versions are performed in MATLAB. 1,000 randomly perturbed ADC output sequences are generated to validate the code hit counters. We then realize both code hit counters in Verilog HDL. After verifying that the Verilog simulation results are consistent with the behavior simulation results, we synthesize the complete code hit counter with TSMC 0.18um mixed signal (1P6M) CMOS process technology through the cell-based flow to realize a macro block that can be easily integrated into an ADC for self-testing or self-calibration applications.