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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Ming-Che Hsieh | en |
| dc.contributor.author | 謝明哲 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:44:16Z | - |
| dc.date.available | 2013-08-20 | |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-19 | |
| dc.identifier.citation | [1] Channel Models for Fixed Wireless Applications, IEEE 802.16 Broadband Wireless Access Working Group, 802.16.3c-01/29r4, July 2001.
[2] V. Shtrom, J. Tellado, and Paulraj, “Designing MIMO Systems for Reliable Coverage in Non-LOS Wireless Links,” RF Design, vol. 25, no. 10, pp. 32-44, October 2002. [3] P. Dent, G.E. Bottomley, and T. Croft, “Jakes Fading Model Revisited,” IEE Electronics Letters, vol. 29, no. 13, pp.1162-1163, June 1993. [4] T. M. Schmidl and D.C. Cox, “Robust Frequency and Timing Synchronization for OFDM,” IEEE Tans. on Communications, vol. 45, no. 12, pp. 1613-1621, Dec. 1997. [5] P.-Y. Tsai, H.-Y. Kang, and T.-D. Chiueh, “Joint Weighted Least Squares Estimation of Frequency and Timing Offset for OFDM Systems over Fading Channels,” Proc. of IEEE Vehicular Technology Conference, vol. 4, pp. 2543-2547, April 22-25, 2003. [6] H.Y. Kang, “Design and Implementation of an MC-CDMA Baseband Transceiver,” Master Thesis, Dept. of Electrical Engineering, National Taiwan University, Taipei, Taiwan, Jun. 2003. [7] S. Barbarossa, M. Pompili, and G.B. Giannakis, “Channel-Independent Synchronization of Orthogonal Frequency Division Multiple Access Systems,” IEEE Journal on Selected Areas in Communications, vol. 20, no. 2, pp. 474-486, February 2002. [8] G. Santella, “A Frequency and Symbol Synchronization System for OFDM Signals: Architecture and Simulation Results,” IEEE Trans. Vehicular Technology, vol. 49, no.1, pp.254-275, January 2000. [9] B.G. Yang, Z.X. Ma, and Z.G. Cao, “ML-Oriented DA Sampling Clock Synchronization for OFDM Systems,” Proc. of IEEE International Conference on Communication Technology, vol.1, pp. 781-784, August 2000. [10] B.G. Yang, K.B. Letaief, R.S. Cheng, and Z.G. Cao, “Timing Recovery for OFDM Transmission,” IEEE Journal on Selected Areas in Communications, vol. 18, no. 11, pp. 2278-2291, November 2000. [11] P.-Y. Tsai and T.-D. Chiueh, “Frequency-Domain Interpolation based Channel Estimation in Pilot-Aided OFDM Systems,” Proc. of IEEE 59th Vehicular Technology Conference, vol. 1, pp. 420–424, May 2004. [12] Texas Instruments, TMS320C6000 CPU and Instruction Set, Literature number SPRU189F, Oct. 2000. [13] Texas Instruments, TMS320C6000 DSP Cache User’s Guide, Literature number SPRU656A, May 2003. [14] Texas Instruments, Code Composer Studio User’s Guide, Literature number SPRU328B, Feb.2000. [15] Texas Instruments, TMS320C6000 Code Composer Studio Getting Started Guide, Literature number SPRU509D, Aug. 2003. [16] Texas Instruments, TMS320C6000 Progammer’s Guide, Literature number SPRU198G, Oct.2002. [17] Texas Instruments, TMS320C64x DSP Library Programmer’s Reference, Literature number SPRU565B, Oct. 2003. [18] M. H. Wu, “A Reconfigurable Architecture for OFDM-based Wireless Communication Systems,” Master thesis, Dept. of Electrical Engineering, National Taiwan University, Taipei, Taiwan, June 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46967 | - |
| dc.description.abstract | 本論文根據802.16-2004 OFDM標準提出一用戶端基頻實體層收發機之架構。在基頻通道模型包含SUI通道模型、加成性白色高斯雜訊、載波頻率飄移以及取樣時脈飄移的前提下，接收機則運用合適的演算法來進行符元邊界偵測、載波頻率飄移和取樣時脈之偵測補償、頻率等化器與內插器等來進行資料回復。進一步在德州儀器(TI)的TMS320C6416 DSP來模擬軟體實現，並藉由一連串的軟體開發流程來降低內接收機所需運行的時脈數以達到及時運算的要求。 | zh_TW |
| dc.description.abstract | In this Thesis, we propose a baseband physical layer transceiver architecture according to the 802.16-2004 OFDM specifications. The baseband channel model is defined according to the SUI channel model, with Additive White Gaussian Noise (AWGN), carrier frequency offset, and sampling clock offset. To recover the data, suitable algorithms are used to detect the symbol boundary, to estimate and compensate carrier frequency offset and sampling clock offset, to interpolate, and to perform the frequency-domain equalization in the receiver. Moreover, the TMS320C6416 DSP of Texas Instruments (TI) is used in software implementation. By a sequence of code development flow, the operation cycles are reduced and the inner receiver is able to meet the real time requirement. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:44:16Z (GMT). No. of bitstreams: 1 ntu-99-R97943025-1.pdf: 2807721 bytes, checksum: d8815e87b46182a89042d9a0cf1a2321 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | TABLE OF CONTENTS
ABSTRACT .................................................................................................... i LIST OF FIGURES ................................................................................................. vii LIST OF TABLE ...................................................................................................... xi CHAPTER 1 INTRODUCTION………… ...................................................... 1 1.1 Motivation.................................................................................................. 1 1.2 Introduction of 802.16-2004 and 802.16e Wimax Networks ....................... 2 1.3 Thesis Organization .................................................................................... 3 CHAPTER 2 PHYSICAL LAYER SPECIFICATION AND TRANSMITTER ARCHITECTURE ............................................................................................... 5 2.1 Introduction of Physical Layer Specifications ............................................. 5 2.2 Introduction of Orthogonal Frequency Division Multiplexing and System Parameters..................................................................................................... 6 2.2.1 Introduction of Orthogonal Frequency Division Multiplexing System 6 2.2.2 Introduction of OFDM Symbol and System Parameters ..................... 7 2.3 Transmitter System Architecture............................................................... 10 2.3.1 Scrambler ........................................................................................ 10 2.3.2 Reed-Solomon Encoder ................................................................... 11 2.3.3 Convolutional Encoder .................................................................... 11 2.3.4 Interleaver ....................................................................................... 12 2.3.5 Data Modulation .............................................................................. 13 2.3.6 Pilot Modulation .............................................................................. 13 2.3.7 Symbol Shaping .............................................................................. 15 2.3.8 Preamble Modulation....................................................................... 15 2.3.9 Transmission Type ........................................................................... 17 2.4 Frame Structure and Packet Format .......................................................... 19 CHAPTER 3 BASEBAND CHANNEL MODEL .......................................... 21 3.1 Stanford University Interim Channel Model ............................................. 21 3.2 Baseband Channel Model ......................................................................... 22 3.2.1 Baseband Channel Model Architecture ............................................ 22 3.2.2 Rayleigh Fading and Ricean Fading ................................................. 24 3.2.3 Additive White Gaussian Noise ....................................................... 29 3.2.4 Carrier Frequency Offset ................................................................. 30 3.2.5 Sampling Clock Offset..................................................................... 31 CHAPTER 4 RECEIVER ARCHITECTURE ................................................ 33 4.1 Receiver Overview ................................................................................... 33 4.2 Initial Synchronization ............................................................................. 34 4.2.1 Coarse Symbol Boundary Detection ................................................ 34 4.2.2 Fractional Part Carrier Frequency Offset Acquisition ....................... 39 4.2.3 Integer Part Carrier Frequency Offset Acquisition and Fine Symbol Boundary Detection ............................................................................ 40 4.3 Fast Fourier Transform ............................................................................. 42 4.4 CFO and SCO Tracking Loop .................................................................. 48 4.4.1 Joint Weighted Least Squares Estimator ........................................... 48 4.4.2 Loop Filter....................................................................................... 50 4.4.3 Compensation for CFO and SCO ..................................................... 51 4.5 Channel Estimation and Frequency-domain Equalizer .............................. 55 4.5.1 Channel Estimation and Interpolator ................................................ 55 4.5.2 Frequency-domain Equalizer ........................................................... 58 4.5.3 Phase Modification .......................................................................... 58 4.5.4 Slicer ............................................................................................... 58 4.6 Simulation Results ................................................................................... 59 4.6.1 Performance without Doppler Effect ................................................ 59 4.6.2 Performance with Doppler Effect ..................................................... 61 4.6.3 Performance with CFO and SCO ..................................................... 63 4.6.4 Total Performance of the Inner Receiver .......................................... 64 CHAPTER 5 DSP IMPLEMENTATION ....................................................... 67 5.1 TMS320C6416 DSP Chip ........................................................................ 67 5.1.1 TMS320C6416 Feature .................................................................... 67 5.1.2 Central Processing Unit Features ..................................................... 69 5.1.3 Cache Memory Architecture Overview ............................................ 73 5.2 TI’s Code Development Environment ....................................................... 74 5.3 Code Development Flow .......................................................................... 76 5.3.1 Compiler Optimization Options .................................................... 79 5.4 DSP Implementation ................................................................................ 80 5.4.1 System Performance without Optimization ...................................... 82 5.4.2 Floating Point to Fixed Point ........................................................... 82 5.4.3 Computation Reduction ................................................................... 84 5.4.4 Intrinsic and DSP Library Using ...................................................... 85 5.4.5 Final Results and Comparison ......................................................... 88 CHAPTER 6 CONCLUSION AND FUTURE WORK .................................. 91 REFERENCE ................................................................................................. 93 | |
| dc.language.iso | en | |
| dc.subject | 數位訊號處理器 | zh_TW |
| dc.subject | 基頻接收機 | zh_TW |
| dc.subject | 802.16-2004 | zh_TW |
| dc.subject | 軟體實現 | zh_TW |
| dc.subject | Digital Signal Processor | en |
| dc.subject | Baseband Receiver | en |
| dc.subject | 802.16-2004 | en |
| dc.subject | Software Implementation | en |
| dc.title | IEEE 802.16-2004 基頻接收機之數位訊號處理器軟體實現 | zh_TW |
| dc.title | DSP Software Implementation of an IEEE 802.16-2004 Baseband Receiver | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),闕志達(Tzi-Dar Chiueh),熊博安(Pao-Ann Hsiung) | |
| dc.subject.keyword | 802.16-2004,基頻接收機,數位訊號處理器,軟體實現, | zh_TW |
| dc.subject.keyword | 802.16-2004,Baseband Receiver,Digital Signal Processor,Software Implementation, | en |
| dc.relation.page | 93 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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