應用延遲鎖定迴路之多相位與去偏斜時脈產生器

Abstract

延遲鎖定迴路(DLL)廣泛地被應用於多相位時脈產生器。傳統的延遲鎖定迴路只對齊輸出的時脈和輸入的時脈。因此，延遲線因為製程、電壓和溫度變化而造成的不匹配，無法被迴路所修正，使得輸出之多相位準確度變差。為了解決這問題，分散式延時鎖定迴路被提出，同時達到了低抖動和高相位準確度。

然而，相位偵測器(PD)之間的不匹配仍會造成輸出相位的不準確。為了解決這問題，平均相位偵測器的技巧被我們提出且應用在原本的分散式延時鎖定迴路上。修改後的分散式延時鎖定迴路實現在65-nm CMOS製程中。消耗16 mW及使用1.45 V之供給電壓。使用了0.95×0.95 mm2的晶片面積。 我們提出一個產生任意且寬域延遲之全數位去偏斜時脈產生器來達到穩定又快速的鎖定。在高速系統中，時脈偏斜是個很大的問題，尤其因為時脈愈來愈快，偏斜量可能是好幾個時脈週期。所設計之時脈產生器實現於0.18-

DLLs are widely used in the multiphase clock generation. The conventional DLL only aligns the phase of the delayed output clock with the reference clock; therefore, the device mismatches induced by the process, voltage and temperature variation are not corrected by the loop and degrade the phase accuracy among each output clock. To mitigate the design constraint, a distributed DLL (DDLL) was proposed to achieve low jitter and high phase accuracy simultaneously. However, the mismatches in PDs still degrade the phase accuracy among each output clock. To lessen the effect of the mismatch of the PDs, a PD rotation technique is proposed in this work along with the distributed DLL technique to further reduce the phase mismatch. The proposed DDLL is designed and fabricated in a 65-nm CMOS process. The experimental results indicate that the multiphase clock generator with self-calibration circuits is able to work with a power dissipation of 16 mW in a 1.45V power supply. The chip size is 0.95×0.95 mm2. An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-