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標題: | 雙圖案微影技術之晶片設計方法 Design Methodology for Double Patterning Technology |
作者: | Chin-Hsiung Hsu 許欽雄 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 雙圖案微影技術,可製造性,實體設計,繞線,超大型積體電路, Double Patterning,Manufacturability,Physical Design,Routing,VLSI, |
出版年 : | 2010 |
學位: | 博士 |
摘要: | 隨著積體電路技術的不斷進步,由於可印刷性和可製造性的問題,微影製程遇到了瓶頸。雙圖案微影技術近來備受注目而且被視為最適用於32 奈米製程的技術,因為雙圖案微影技術可以在目前的基礎設施上,加大最小圖案距離(高達二倍),從而將193i 光源波長的使用延伸到32 奈米節點,甚至可能到16 奈米節點。雙圖案微影技術將一個佈局分解到二個光罩上,然後使用雙重圖案曝光技術以加大最小圖案距離並提升圖案的可印刷性。雙圖案微影技術的圖案衝突(conflict)是指佈局無法被完整地分解;雙圖案微影技術的縫合圖案(stitch)是指一個佈局圖案被切割成二個圖案並分解到不同的光罩上。但是,現有的設計流程與雙圖案微影技術無法相容,因為所產生的電路佈局無法完整地分解到二片光罩上。因此,開發相容於雙圖案微影技術的設計流程是非常重要的,尤其是那些與雙圖案微影技術強烈相關的設計步驟,包括:(1)以佈局遷移為基礎的電路單元設計、(2)全域繞線、以及(3)細部繞線。此外,光罩成本的倍數成長也是雙圖案微影技術所引起一個重要的問題,所以我們的相容於雙圖案微影技術的設計流程會最小化光罩的使用量。
當積體電路的微影製程不斷演進,手動設計電路單元卻因為非常花時間而漸漸跟不上微影製程的腳步,因此,以佈局遷移為基礎的電路單元設計變得非常熱門。佈局遷移和雙圖案微影技術的佈局分解成為兩個密切相關的問題。因此,我們提出文獻上第一個同時完成電路佈局的遷移和分解之問題,並使用整數線性規劃方法以得到最終電路佈局。 晶片繞線是一個非常複雜的過程,現代的晶片繞線通常分為全域繞線和細部繞線;全域繞線先產生一個概略的繞線路徑,而細部繞線決定實際的詳細繞線路徑,也就是產生電路佈局。全域繞線是一個重要的實體設計步驟,但現有的全域繞線的繞線模型沒有考慮雙圖案微影技術的影響,也忽略了多重金屬層需要合理的導通孔(via)分佈。因此,我們提出了一個新的全域繞線模型與全域繞線器,並考慮合理的導通孔分布與雙圖案微影技術的影響。 在考量雙圖案微影技術的情況下,細部繞線是很重要的一環,因為它決定金屬層的佈局;同時,細部繞線也提供了一個很好的機會,去減少雙圖案微影技術所使用的光罩數量。我們提出了第一個在雙圖案微影技術下,讓不同的晶片設計能夠共享光罩的設計方法,以達到減少光罩使用量之目的。我們所提出的設計方法首先設計好模版光罩再完成考慮模版光罩的細部繞線,而且我們的細部繞線演算法所產生的繞線結果可以符合雙圖案微影技術與模版光罩的限制。 實驗結果顯示,相對於傳統的設計流程,我們的相容於雙圖案微影技術的設計流程所得到的結果擁有較小的電路佈局面積、較少的縫合圖案與較短的線長,雖然使用較多的導通孔與運算時間,但皆在合理範圍之內。此外,我們的相容於雙圖案微影技術的設計流程可以得到無衝突(conflict-free)的電路佈局,並總共節省了八片光罩;而傳統的設計流程不僅產生的電路佈局有衝突,也無法節省任何光罩。結果顯示了我們的相容於雙圖案微影技術的設計流程的有效性和我們所提的相關技術與現有的電子設計自動化(EDA)工具的相容性。 As IC technology continues to advance, lithography process meets the bottleneck due to printability and manufacturability. Double patterning technology (DPT) has recently gained much attention and is viewed as the most promising solution for the sub-32-nm node process, since it can increase the half-pitch resolution by up to two times using current infrastructures, thereby extending 193i wavelength beyond the 32-nm node and potentially down to the 16-nm node. DPT decomposes a layout into two masks and applies double exposure patterning to increase the pitch size and thus printability; conflict arises if layouts are not decomposable, and a stitch is induced if two touching sub-patterns of the same pattern are decomposed into different masks. However, the existing design flow is not compatible with DPT since resulting layouts with patterns are not decomposable. Therefore, it is desirable to develop a DPT-compliant design flow that focuses on strongly DPT-related stages, including (1) layout-migration-based cell design, (2) global routing, and (3) detailed routing. Besides, the cost of doubling masks is also an important problem for DPT, so our DPT-compliant design flow would minimize the number of masks for DPT. Layout-migration-based cell design becomes very popular as IC technology continues to advance very quickly and manual cell design is very time-consuming. Layout migration and DPT layout decomposition become two closely related problems for DPT-aware cell design. Therefore, we present the first algorithm in the literature for the simultaneous layout migration and decomposition (SMD) problem. Our algorithm first constructs a potential conflict graph and DPT-aware constraint graphs, and then applies integer linear programming (ILP) corresponding to the graphs to obtain a decomposed and migrated layout. We further present an effective graph-based reduction technique to prune the ILP solution space. In addition, we present an approach to generate DPT-aware standard cells by considering the DPT effects on the cell boundaries to handle the DPT issues in the weakly-pattern-related placement stage. Routing is a very complex process in a modern chip, so routing is often divided into global routing and detailed routing; global routing generates a loose route for each net while detailed routing finds the actual geometric layout of nets. Global routing is an important step for physical design, but existing global routing congestion models ignore DPT effects and reasonable via usage for routing through multiple metal layers. Such simplified models would easily cause fatal routability and DPT-compliant problems in the subsequent detailed routing. To remedy this deficiency, a more effective congestion metric that considers both the DPT effects and the reasonable via usage for global routing is presented. With this metric, we develop a new multi-layer global router that features two novel routing algorithms, namely aerial-monotonic routing and escaping-point routing. Detailed routing is an important step to make layouts DPT-compliant since it decides actual geometric layout of nets; besides, it also has an opportunity to reduce the number of masks for DPT. We proposes the first mask-sharing methodology for DPT, which can share masks among different designs, to reduce the number of costly masks for double patterning. The design methodology consists of two tasks: template-mask design and template-mask-aware detailed routing. A graph matching-based algorithm is developed to design a flexible template mask that tries to accommodate as many design patterns as possible. We also present a template-mask- aware detailed routing (TMR) algorithm, focusing on DPT-related issues to generate routing solutions that satisfy the constraints induced from double pattern ing and template masks. Experimental results show that, compared with the non-DPT-compliant design flow, our DPT-compliant design flow can achieve smaller layout area, fewer stitches, and shorter wirelength with reasonable via and runtime overheads. In addition, our DPT-compliant design flow can obtain conflict-free layouts and totally save eight masks for DPT while the non-DPT-compliant design flow cannot. The results show the effectiveness of our DPT-compliant design flow and the compatibility between our DPT-related techniques and existing electronic design automation (EDA) tools. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46518 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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