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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Feipei, Lai) | |
| dc.contributor.author | Chi-Wei Lin | en |
| dc.contributor.author | 林志威 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:56:46Z | - |
| dc.date.available | 2015-07-30 | |
| dc.date.copyright | 2010-07-30 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-28 | |
| dc.identifier.citation | [1] A. P. Chandrakasan and R. W. Brodersen, 'Minimizing power consumption in digital CMOS circuits,' Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
[2] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, 1 ed. Norwell, MA and AH Dordrecht, The Netherlands: Kluwer Academic Publishers, 1995. [3] Komoto, E.; Homma, T.; Nakamura, T.; , 'A high-speed and compact-size JPEG Huffman decoder using CAM,' VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on , vol., no., pp. 37- 38, 19-21 May 1993 [4] Wei, B.W.Y.; Tarver, R.; Kim, J.-S.; Ng, K.; , 'A single chip Lempel-Ziv data compressor,' Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on , vol., no., pp.1953-1955 vol.3, 3-6 May 1993 [5] Nakanishi, M.; Ogura, T.; , 'A real-time CAM-based Hough transform algorithm and its performance evaluation,' Pattern Recognition, 1996., Proceedings of the 13th International Conference on , vol.2, no., pp.516-521 vol.2, 25-29 Aug 1996 [6] Meribout, M.; Ogura, T.; Nakanishi, M.; , 'On using the CAM concept for parametric curve extraction,' Image Processing, IEEE Transactions on , vol.9, no.12, pp. 2126- 2130, Dec 2000 [7] K. Pagiamtzis and A. Sheikholeslami, 'Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,' IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006. [8] K. J. Schultz, 'Content-addressable memory core cells: a survey,' Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997. [9] G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, '200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,' in Proceedings of the IEEE Custom Integrated Circuits Conference, 2003, pp. 387-390. [10] I. Arsovski, T. Chandler, and A. Sheikholeslami, 'A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,' IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003. [11] I. Arsovski and A. Sheikholeslami, 'A current-saving match-line sensing scheme for content-addressable memories,' in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2003, pp. 304-494 vol.1. [12] I. Arsovski and A. Sheikholeslami, 'A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,' IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1958-1966, Nov. 2003. [13] K. Pagiamtzis and A. Sheikholeslami, 'A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,' IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004. [14] S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, 'A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router,' IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853-861, Apr. 2005. [15] K. Cheong, Q. Shaolei, and A. Mason, 'A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead,' in Proceedings of the International Symposium on Circuits and Systems (ISCAS), 2004, pp. II-753-6 Vol.2. [16] C.-S. Lin, J.-C. Chang, and B.-D. Liu, 'A low-power precomputation-based fully parallel content-addressable memory,' IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 654-662, Apr. 2003. [17] S.-J. Ruan, C.-Y. Wu, and J.-Y. Hsieh, 'Low Power Design of Precomputation-Based Content-Addressable Memory,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3, pp. 331-335, Mar. 2008. [18] C.-Y. Wu, S.-f. Ruan, C.-K. Cheng, and M.-B. Lin, 'A new Block-XOR precomputation-based CAM design for low-power embedded system,' in IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, pp. 1-4. [19] J.-Y. Hsieh and S.-J. Ruan, 'Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm,' in Asia and South Pacific Design Automation Conference (ASPDAC), 2008, pp. 316-321. [20] Echeverria, P.; Ayala, J.L.; Lopez-Vallejo, M.;, 'A banked precomputation-based CAM architecture for low-power storage-demanding applications,' Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean , vol., no., pp.57-60, 16-19 May 2006. [21] Echeverria, P.; Ayala, J.L.; Lopez-Vallejo, M.;, 'Leakage Energy Reduction in Banked Content Addressable Memories,' Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , vol., no., pp.1196-1199, 10-13 Dec. 2006. [22] Sebastian Ang, Chin-Hung Peng, Jürgen Kemper, Uwe Schwiegelshohn and Feipei Lai, “'An Enhanced Low-Power Precomputation-Based Content-Addressable Memory Architecture”,” The 16th IFIP/IEEE International Conference on Very Large Scale Integration, Rhodes Island, Greece, Oct. 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46177 | - |
| dc.description.abstract | 因為內容可定址記憶體廣泛的應用而且可以實做一個查找表功能在一個時脈週期內完成。內容可定址記憶體可以平行比較輸入的搜尋資料和儲存的資料，以提供高速的資料搜尋運作。如果資料搜尋成功代表搜尋的資料和儲存的資料是相符合的，然後內容可定址記憶體會輸出符合資料的位址。在論文中我們提出一個新的架構，應用在預先計算型內容可定址記憶體，其包含了低功率和低消耗的特色。這新的架構結合了關聯度方法和分區方法。結合的結果造成參數記憶體的空間消耗減少，更可以有效的功率節省。經過實驗模擬顯示在功率的消耗上，我們提出的架構相較於ones count預先計算型內容可定址記憶體架構減少47%的功率而在面積的消耗上減少25%，不過有一點延遲產生因為額外的電路設計。 | zh_TW |
| dc.description.abstract | Content addressable-memory (CAM) can be used in wide application and implements the lookup- table function within a single clock cycle. CAM compares input searched data with its stored data parallel that provide high-speed data searched operation. If data search is successful, which indicates that a stored data matches the search word, then CAM outputs the address of the matching word. This thesis presents a novel architecture for precomputation-base content addressable memory (PB-CAM) that includes low power, and low cost characters. The new architecture combines the architectural design technique of associative scheme as well as the banked approach. The experimental results showed that the proposed architecture average reduced by 47% power than the ones count PB-CAM architecture and average reduced by 25 % in chip area reduction while a minimal increase of latency that is caused by the additional circuit design. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:56:46Z (GMT). No. of bitstreams: 1 ntu-99-R97922075-1.pdf: 1914641 bytes, checksum: 54c6fb71a280d959931ee3383a541794 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 摘要 iii Abstract iv Contents v List of Figures vii List of Tables viii Chapter 1 Introduction 1 1.1 Power Dissipation of CMOS Circuit 1 1.1.1 Dynamic Power Dissipation 2 1.1.2 Short-Circuit Power Dissipation 2 1.1.3 Leakage Power Dissipation 3 1.2 Concept of Content Addressable Memory 4 1.2.1 Content Addressable Memory Overview 4 1.2.2 Applications of Content Addressable Memory 5 Chapter 2 CAM Basic and Related Work 8 2.1 CAM Cell 9 2.2 Operation of a CAM Cell 11 2.2.1 Write Operation of a CAM Cell 12 2.2.2 Read Operation of a CAM Cell 13 2.2.3 Search Operation of a CAM Cell 14 2.3 Precomputation Scheme 15 2.4 Motivation and Objective 16 Chapter 3 Proposed Approach 18 3.1 Preliminary Work on PB-CAM 18 3.1.1 Ones Count Approach 18 3.1.2 Block-XOR Scheme 21 3.1.3 Gate-Block Selection Algorithm 24 3.2 Proposed Hybrid PB-CAM Concept 26 3.2.1 Banked approach 26 3.2.2 Parameter-Based Bank Selection Method 28 3.2.3 Parity Based Encoding approach 29 3.2.4 Associative Parameter Scheme 31 Chapter 4 Experimental Results 33 4.1 Experimental Environment 33 4.2 Power Consumption 34 4.2 Latency 35 4.2 Area 37 Chapter 5 Conclusion 39 References 40 | |
| dc.language.iso | en | |
| dc.title | 分區關聯度混合式架構應用在預先計算型內容可定址記憶體 | zh_TW |
| dc.title | Banked-Associative Hybrid Architecture for Precomputation-Based Content-Addressable Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 許孟超(Mon-Chau, Shie),阮聖彰(Shanq-Jang, Ruan),蔡坤霖(Kun-Lin, Tsai),林振群(JenChiun,Lin) | |
| dc.subject.keyword | 內容可定址記憶體,預先計算,低功率,低成本,分區關聯度方法, | zh_TW |
| dc.subject.keyword | content addressable memory (CAM),precomputation,low power,low cost,banked-associative approach, | en |
| dc.relation.page | 42 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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| ntu-99-1.pdf 目前未授權公開取用 | 1.87 MB | Adobe PDF |
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