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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北(Ruey-Beei Wu) | |
| dc.contributor.author | Fu-Sheng Chang | en |
| dc.contributor.author | 張復勝 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:27:57Z | - |
| dc.date.available | 2012-08-21 | |
| dc.date.copyright | 2009-08-21 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-20 | |
| dc.identifier.citation | [1] International Technology Roadmap for Semiconductors. (http://www.itrs.net/)
[2] M. Leone, “The radiation of a rectangular power-bus structure at multiple cavity-mode resonances,” IEEE Trans. Electromagn. Compat., vol. 45, no. 3, pp. 486-492, Aug. 2003 [3] H. Shim and T, H. Hubing, “A closed-form expression for estimating radiated emissions from the power planes in a populated printed circuit board,” IEEE Trans. Electromagn. Compat., vol. 48, no. 1, pp. 74-81, Feb. 2006 [4] 鍾怡燕，利用共平面電磁能隙結構達成電源層雜訊抑制之特性分析與設計，國立台灣大學碩士論文，2007年6月 [5] 王建霖，利用共平面電磁能隙結構達成寬頻接地雜訊抑制之系統化設計，國立台灣大學碩士論文，2006年6月 [6] S. H. Hall, G. W. Hall, and J. A. McCall, “High-Speed Digital System Design,” John Wiley & Sons, Inc., 2000, Chapter 4 [7] Y. Chen, Z. Wu, A. Agrawal, Y. Liu, and J. Fang, “Modeling of delta-I noise in digital electronics packaging,” in 1994 IEEE Multi-Chip module Conf., pp. 126-131,Santa Cruz, CA, Mar. 1994. [8] S. Van den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, “Study of the ground bounce caused by power plane resonances,” IEEE Trans. Electromagn. Compat., vol. 40, pp. 111-119, May 1998. [9] C. T. Wu, G. H. Shiue, S. M. Lin, and R. B. Wu, “Composite effects of reflections and ground bounce for signal line through a split power plane,” IEEE Trans. Adv. Packag., vol. 25, pp. 297-301, May 2002. [10] I. Ndip, F. Ohnimus, S. Guttowski, H. Reichl, “Minimizing electromagnetic interference in power-ground cavities,” Electrical Design of Advanced Packaging and System Symposium, 2008. [11] J. M. Hobbs, H. Windlass, V. Swaminathan, and L. Smith, “A methodology for the placement and optimization of decoupling capacitors for gigahertz systems,” in 13th Int’l Conf. VLSI Design, pp. 156-161, Jan. 2000. [12] K. B. Wu, A.S. Liu, G. H. Shiue, C. M. Lin, and R. B. Wu, “Optimum for the locations of decoupling capacitors in suppressing the ground bounce by Genetic Algorithm,” in Progress in Electromagnetics Reserch Symposium (PIERS), pp. 411-415, Hangzhou, Zhejiang, China, Aug. 22-26, 2005. [13] J. M. Hobbs, H. Windlass, V. Sindaram, S. Chun, G. E. White, M. Swaminathan, and R. Tummala, “Simultaneous switching noise suppression for high speed systems using embedded decoupling,” in Proc. 51st Electronic Comp. Technol. Conf., Orlando, pp. 339-343, May 2001. [14] V. Ricchiuti, “Power bus signal integrity improvement and EMI mitigation high-speed digital PCBs with embedded capacitance,” IEEE Trans. Mobile Computing., vol. 2, no. 4, Oct.-Dec. 2003. [15] R. K. Ulrich and L. W. Schaper, Integrated Passive Component Technology, New York: IEEE and Wiley Intersci., 2003. [16] S, Shahparnia, O. M. Ramahi, “Miniaturized electromagnetic bandgap structures for ultra-wide band switching noise mitigation in high-speed printed circuit boards and packages,” in Proc. 13th Topical Meeting Electrical erformance Electronic Packaging, Portland, OR, pp. 211-214, Oct. 25-27, 2004. [17] D. Pozar, “Microwave Engineering,” 2nd ed., New York Wiley, 1998 [18] S. Van den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, “Study of the ground bounce cased by power plane resonances,” IEEE Trans. Electromagn. Compat., vol. 40, pp. 111-119, May 1998. [19] D. K. Cheng, “Field and Wave Electromagnetics,” 2nd ed., Chapter 10, Addison-Wesley, 1989 [20] F. Haga, K. Nakano, and O. Hashimoto, “Reduction in radiated emission by symmetrical power-ground stack-up PCB with no open edge,” in Proc. IEEE Int. Symp. Electromag. Compat., Minneapolis, MN, pp. 262-267, Aug. 2002. [21] J. S. Pak, J. Lee, H. Kim, and J. Kim, “Prediction and verification of power/ground plane edge radiation excited by through-hole signal via based on balanced TLM and via coupling model,” 2003 IEEE Proc. Topical Meeting on Electrical Performance of Electronic Packag., pp. 181-184, Oct. 2003. [22] T. Fischer, M. Leone, M. Albach, “An analytical model for studying the electromagnetic radiation of power-bus structure,” Proc. of IEEE EMC Symposium, pp. 225-230, 2003. [23] R. Yang, M. D. Rotaru, H. Kuruveettil, D. Pinjala, and M. K. Iyer, “Radiation from arbitrary power/ground plane pair structure,” in Proc. of 7th Electronic Packaging Technology Conf, 2005. [24] X. Yee, D. M. Hockanson, M. Li, Y. Ren, W. Chi, J. L. Drewniak, and R. E. DuBroff, “EMI mitigation with multilayer power-bus stacks and via stitching of reference planes,” ” IEEE Trans. Electromagn. Compat., vol. 43, pp. 538-548, Nov. 2001. [25] C. A. Balanis, Antenna Theory – Analysis and Design, 2nd ed.,Chapter 14, John Wiley & Sons, Inc.,1997. [26] R. F. Harrington, Time-Harmonic Electromagnetic Fields, A Classic Reissue, Chapter 5, John Wiley & Sons, Inc.,2001 [27] R. E. Collins, Field Theory of Guided Waves, 2md ed.,IEEE Press, 1991, Chapter 4. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45572 | - |
| dc.description.abstract | 本論文主要內容是針對多層板電源接地平面所造成的電磁干擾問題做探討。在高速數位電路中，由於許多訊號線穿層或跨槽線的情況引發接地彈跳雜訊，使電磁波在層板間來回傳播與反射，並於邊緣產生電磁輻射雜訊，即電磁干擾。本文使用空腔共振器模型與共模�差模模態輻射模型解釋多層板輻射機制，並推導出一估算兩模態輻射量差值，即最大功率抑制輻射量。為了有效抑制多層板邊緣等效磁流所造成的電磁輻射問題，本文提出利用不同接地連通柱擺放方式，如一圈連通柱擺放、兩圈連通柱平行擺放以及兩圈連通柱交錯擺放方式，比較其抑制差模模態輻射的效果，並透過解析方法，分析如何使用最低成本擺放接地連通柱達到最佳輻射抑制效果。對於一圈連通柱擺放設計，其可抑制到40dB的EMI輻射量；而兩圈接地連通柱擺放可抑制到66dB以上的EMI輻射量。最後，利用電磁模擬軟體與GHz橫向電磁波傳輸室量測驗證此設計的準確性。 | zh_TW |
| dc.description.abstract | This thesis focuses on the problem of Electromagnetic Interference（EMI）of Printed Circuit Board（PCB）power/ground planes, which is a crucial issue to the whole system stability in high speed digital circuit. The primary noise of power/ground planes which arises from current flowing through a via or the signal trace crossing slot lines is the ground bounce. The electromagnetic waves reflecting back and forth from edges of the substrate generate a standing wave, which gives rise to radiated emission, and is often identified as EMI. The cavity resonator model together with a new even/odd mode radiation model is proposed to explain the radiated emission mechanism. The maximum power suppression between even and odd mode radiation is derived. This thesis then employs one way of using the shorting vias to suppress the odd mode radiation resulting from the PCB edges. By analytical methods, several designing methods of shorting vias placement, including 1-column vias, 2-column parallel vias and 2-column interlacing vias are presented. EMI suppression is above 40dB and 66dB for 1-column and 2-column vias design respectively. Finally, EM simulation tool “HFSS” and GTEM Cell measurement are used to validate the accuracy of the design. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:27:57Z (GMT). No. of bitstreams: 1 ntu-98-R96942001-1.pdf: 2556843 bytes, checksum: 22cf8a6ce52e3fd1b74b0a2dcf5d998d (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 致 謝 i
摘 要 ii Abstract iii 目 錄 iv 圖 例 vi 表 格 ix 表 格 ix 第一章 研究動機與簡介 1 1-1 研究動機 1 1-2 文獻回顧與探討 2 1-3 章節概要 5 1-4 貢獻 6 第二章 多層式電源接地平面輻射場分析 12 2-1 平行金屬板簡介 12 2-2 遠場輻射機制與電磁場分析 14 2-3 遠場總輻射功率分析 16 第三章 多層式電源接地平面共模與差模輻射分析 21 3-1 共模與差模模態輻射機制 21 3-2 共模與差模模態總輻射功率分析 21 3-3 平均等效角度θeff 25 3-4 電磁模擬與理論分析驗證 28 第四章 利用接地連通柱抑制電磁輻射之擺放分析 38 4-1 接地連通柱散射場簡介 38 4-2 格林函數之簡化 39 4-3 一圈接地連通柱擺放分析 40 4-4 兩圈接地連通柱擺放分析 42 第五章 利用接地連通柱抑制電磁輻射之擺放設計 54 5-1 一圈接地連通柱變數分析與擺放設計 54 5-2 兩圈接地連通柱變數分析與擺放設計 57 5-3 接地連通柱擺放設計準則 59 5-4 電磁模擬與GTEM量測驗證 63 第六章 結論與未來工作 80 6-1 結論 80 6-2 未來工作 81 參考文獻 82 | |
| dc.language.iso | zh-TW | |
| dc.subject | 電磁干擾 | zh_TW |
| dc.subject | 接地彈跳雜訊 | zh_TW |
| dc.subject | 空腔共振器模型 | zh_TW |
| dc.subject | 接地連通柱 | zh_TW |
| dc.subject | cavity resonator model | en |
| dc.subject | shorting vias | en |
| dc.subject | electromagnetic interference | en |
| dc.subject | ground bounce | en |
| dc.title | 多層板電源接地平面電磁干擾分析與利用接地連通柱抑制輻射雜訊之設計 | zh_TW |
| dc.title | EMI Analysis of Multilayer PCB Power/Ground Planes and Radiation Suppression Design by Shorting Vias | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳宗霖(Tzong-Lin Wu),鄭士康(Shyh-Kang Jeng),駱韋仲(Wei-Chung Lo) | |
| dc.subject.keyword | 電磁干擾,接地彈跳雜訊,空腔共振器模型,接地連通柱, | zh_TW |
| dc.subject.keyword | electromagnetic interference,ground bounce,shorting vias,cavity resonator model, | en |
| dc.relation.page | 83 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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