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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Wen-Yu Lin | en |
| dc.contributor.author | 林文昱 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:27:17Z | - |
| dc.date.available | 2010-08-20 | |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-20 | |
| dc.identifier.citation | [1] B. Razavi, “Principles of Data Conversion System Design” Wiley-IEEE Press, 1995.
[2] Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters” Kluwer Academic Publishers, 2003. [3] Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters” Kluwer Academic Publishers, 2003. [4] Kurosawa. N, Kobayashi H, Maruyama. K, Sugawara. H, Kobayashi. K, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 48, Issue 3, March 2001 Pages:261-271. [5] Mikael Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Academic Publishers, 2000. [6] S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan,“A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [7] F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 853–863, Nov. 1995. [8] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques-Part I,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371-379, Dec. 1975. [9] Hae-Seung Lee; Hodges, Dave A. “Self-calibration technique for A/D converters”Circuits and Systems, IEEE Transactions on , Volume: 30 , Issue: 3 , Mar 1983 Pages:188 – 190 [10] M. Shinagawa, Y. Akazawa, and T. Wakiomoto, “Jitter Analysis of High Speed Sampling Systems,” IEEE J. Solid-State Circuits, vol. SC-25, no. 2, pp. 220-224, Feb. 1990 [11] F. Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13um CMOS,” ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002. [12] M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske, “A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13um CMOS,”ISSCC Dig. Tech. Papers, pp. 248-249, Feb. 2007. [13] J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,”IEEE J. Solid-State Circuits, vol.19, No.6, pp. 820-827, Dec 1984 [14] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, Geert Van der Plas, J. Craninckx,“An 820uW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008. [15] J. Craninckx and G. Van der Plas, “A 65fJ/Conversion-Step 0-to-50Ms/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007. [16] A. Shrivastava, “12-bit Non-Calibrating Noise-Immune Redundant SAR ADC for System-on-a-Chip”, Proc. IEEE ISCAS, pp. 1515-1518, May 2006. [17] A. Wada, et al., “A 14mW 10–bit 20–Msample/s ADC in 0.18um CMOS with 61MHz–input,” Proceedings of the 28th Solid-State Circuits Conference, pp. 459-462, Sept. 2002. [18] Hsin-Shu Chen, Bang-Sup Song and Kantilal Bacrania, “A 14b 20MSamples/s CMOS Pipelined ADC,” IEEE Journal of Solid-State Circuits, pp. 997-1001, Jun. 2001. [19] Behzad Razavi, Design of Analog CMOS Integrated Circuits. New-York: McGraw-Hill, 2001. [20] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [21] P. R. Gray, et al., Analysis and Design of Analog Integrated Circuits. New-York: Wiley, 2001. [22] Chun-Cheng Liu, et al., “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process,” IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp. 236-237, Jun. 2008. [23] Joshua J. Kang and Michael P. Flynn, “A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13um CMOS,” IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp. 240-241, Jun. 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45561 | - |
| dc.description.abstract | 本論文闡述一個十位元每秒八千萬次取樣之循序趨近式類比數位轉換器(Successive Approximation Analog-to-Digital Converter)，包含一個不固定基底之二元搜尋電容陣列，並以聯電 90-um CMOS 製程製作。使用此論文所提出電容陣列之類比數位轉換器達到更高的轉換速率以及更低的功率消耗，相較於以往的非二基底循序趨近式類比數位轉換器。並且使用時間交錯式架構 (Time-Interleaved) 更進一步的達到更高的轉換速率。
根據量測結果，本類比數位轉換器之 DNL 為 +0.9/-0.7 LSB，INL 為 +1.2/-1.3 LSB。在 80MS/s，輸入頻率為奈奎斯特頻率的情況下，SFDR 為 58.0dB，SNDR 為 49.3dB。在 1.2 伏特供應電壓下，消耗功率為 2.87mW。 | zh_TW |
| dc.description.abstract | A 10b 80 MS/s CMOS Non-Binary SAR ADC using a non-constant radix binary search capacitor array is demonstrated in a standard 90-nm CMOS process. The ADC with the proposed capacitor array achieves higher conversion rate and lower power consumption compared to the prior non-binary SAR ADC works. Moreover, two-channel timeinterleaved method is utilized to achieve higher conversion rate.
The prototype circuit exhibits an DNL of +0.9/-0.7 LSB and a INL of +1.2/-1.3 LSB. The SNDR and SFDR achieves 49.3 dB and 58.0 dB at 80 MS/s for Nyquist input frequency. The ADC consumes 2.87 mW at 1.2V supply and occupies an active chip area of 0.14 mm2. The FoM is 155.5 fJ/conv.-step at 80 MS/s. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:27:17Z (GMT). No. of bitstreams: 1 ntu-98-R95943126-1.pdf: 4349242 bytes, checksum: 1a8f2a6c4fae44f1bf2c11512aba1e1e (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 誌謝.....................................................i
Abstract................................................ii Table of Contents.......................................iv List of Figures .......................................vii Chapter 1 Introduction ..................................1 1.1 Motivation ..........................................1 1.2 Thesis Organization .................................2 Chapter 2 Fundamentals of Analog-to-Digital Converter....3 2.1 Introduction ........................................3 2.2 The Role Of An ADC ..................................3 2.3 Performance Metrics .................................4 2.3.1 Signal-to-Noise Ratio (SNR) .......................4 2.3.2 Spurious-Free Dynamic Range (SFDR) ................4 2.3.3 Total Harmonic Distortion (THD) ...................5 2.3.4 Signal-to Noise and Distortion Ratio (SNDR) .......5 2.3.5 Effective Number of Bits (ENOB) ...................5 2.3.6 Differential Nonlinearity (DNL) ...................6 2.3.7 Integral Nonlinearity (INL) .......................7 Chapter 3 Time-Interleaved A/D Converter ................8 3.1 Introduction ........................................8 3.2 Time-Interleaved A/D Converter System ...............8 3.3 Channel Mismatch Effects ...........................10 3.3.1 Offset Mismatch Effect ...........................10 3.3.2 Gain Mismatch Effect .............................12 3.3.3 Clock Timing Error Effect ........................13 3.3.4 Combined Channel Mismatch Effect .................15 Chapter 4 Successive Approximation Register (SAR) Analog-to- Digital Converter ......................................18 4.1 Introduction .......................................18 4.2 Successive Approximation Register ADC Architecture .19 4.3 Charge Redistribution SAR ADC Architecture .........20 4.4 Source of Error ....................................22 4.4.1 Capacitor Mismatch ...............................22 4.4.2 Operational Amplifier Gain Error and Offset ......25 4.4.3 Aperture Jitter ..................................25 4.4.4 Charge Injection and Clock Feedthrough ...........27 4.4.5 Leakage Current ..................................28 Chapter 5 Proposed Non-Constant Radix Binary Search Capaci- tor Array ..............................................30 5.1 Introduction .......................................30 5.2 Non-Binary SAR ADC .................................31 5.3 Proposed Non-Constant Radix Binary Capacitor Array .34 5.4 Array Arrangement ..................................36 5.5 System Architecture ................................38 Chapter 6 Circuit Implementation .......................40 6.1 Introduction .......................................40 6.2 Choosing the Size of Unit Capacitor ................40 6.3 Pre-Amplifier ......................................42 6.4 Comparator .........................................43 6.5 Layout Floorplan ...................................43 6.6 Simulation Result ..................................45 Chapter 7 Measurement Result ...........................48 7.1 Introduction .......................................48 7.2 Measurement Setup ..................................48 7.3 Evaluation Board Design ............................49 7.4 Measurement Result .................................54 7.4.1 Static Performance ...............................54 7.4.2 Dynamic Performance ..............................55 7.5 Summary ............................................56 Chapter 8 Conclusion ...................................58 Bibliography ...........................................59 Appendix - System Level Behavior Model .................62 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 十位元 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 循序趨近式類比數位轉換器 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | Low-Power | en |
| dc.subject | Analog-to-digital Converter | en |
| dc.subject | Non-Binary SAR ADC | en |
| dc.subject | 10-bit | en |
| dc.subject | High-Speed | en |
| dc.title | 一個十位元高速低功率之循序趨近式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit High-Speed Low-Power Successive Approximation ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡宗亨,林宗賢,顧孟愷 | |
| dc.subject.keyword | 十位元,類比數位轉換器,循序趨近式類比數位轉換器,高速,低功率, | zh_TW |
| dc.subject.keyword | 10-bit,Analog-to-digital Converter,Non-Binary SAR ADC,High-Speed,Low-Power, | en |
| dc.relation.page | 82 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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