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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃建璋(Jian-Jang Huang) | |
| dc.contributor.author | Shih-Hua Hsiao | en |
| dc.contributor.author | 蕭世驊 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:24:01Z | - |
| dc.date.available | 2010-08-11 | |
| dc.date.copyright | 2010-08-11 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2010-08-06 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45506 | - |
| dc.description.abstract | 在本篇論文中,我們考慮氧化鋅薄膜電晶體操作於載子累積區域,以及氧化鋅薄 膜本身的奈米晶體特性,發展出一套完整的遷移率與電流模型。首先為了觀察氧 化鋅薄膜電晶體的實際特性,我們設計並製做了多種不同的元件,包括氧化鋅電 晶體、氧化鎵鋅電晶體,以及以氧化鎵鋅做為二維電子雲通道的 delta-doping 氧化 鋅薄膜電晶體。透過針對這些元件的量測與特性分析,我們推估出適合氧化鋅薄 膜電晶體的最佳設計,同時驗證薄膜的奈米晶體特性,並且發現在汲極電流對汲 極電壓的關係圖中,這些元件表現出在高溫製程下的電晶體不會發生的 overshoot 現象。我們接著考慮奈米晶粒之間的晶隙影響,發展氧化鋅薄膜電晶體的元件物 理模型。我們成功模擬了閘極電壓與汲極電壓對通道中各點的載子濃度與晶隙能 障的影響,並從載子濃度與晶隙能障在電晶體通道中的分佈,推導出通道整體的 遷移率以及電流的變化。由此模型,我們推論在實驗中發現的 overshoot 現象成因 即來自於奈米晶通道中晶隙能障的存在。從模型中我們發現,通道中的陷阱密度 與晶粒大小,會對 overshoot 的大小產生影響,同時也影響遷移率。我們由此驗證, 由於低溫製程中缺陷密度大,且晶粒較小,氧化鋅薄膜電晶體因而表現出我們所 量測到的特性。 | zh_TW |
| dc.description.abstract | A comprehensive analytical current-voltage model as well as the mobility model of the ZnO-based thin film transistors considering both the carrier accumulation in the channel and the nanocrystalline properties are demonstrated in this work. To observe the device characteristics, various designs of ZnO-based TFTs including ZnO-TFTs, GZO TFTs and GZO delta-doped ZnO TFTs are fabricated and characterized, in which we have found the best design of ZnO-based TFT, verified the nanocrystalline characteristics of the ZnO thin films, as well as observed the overshoots in the ID-VD curves. With the understanding of the devices, the mobility and current-voltage model is then derived considering the carrier concentration and the grain boundary energy barriers throughout the channel modulated by both the vertical and the lateral electric fields in the channel. With the distribution of the carrier concentration and the grain boundaries in the channel, the mobility and current are derived. Utilizing this model, we investigate the influence of the grain boundary trap density and the grain size of the channel material on the ID-VD curves of ZnO-based TFTs, and explains the reasons of the the overshoots in the ID-VD curve, which have been observed in the experiment results. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:24:01Z (GMT). No. of bitstreams: 1 ntu-98-R96941010-1.pdf: 3417558 bytes, checksum: 4ad59adee3157be3f7695be8f4b932c1 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Chapter 1. Introduction........................... 1
1.1 Research Backgrounds ........................... 1 1.2 Research Motivations .............................. 3 1.3 Thesis Structure ................................... 6 Chapter 2. Theory and Literatures Review ................. 7 2.1 Thin film transistors.......................... 7 2.1-1 MOSFET .................................. 8 2.1-2 TFT .................................... 18 2.1-3 Oxide Semiconductor TFT.......................... 22 2.1-4 Delta-doped FETs............................... 23 2.2 ZnO-based material properties ........................... 25 2.3 Polycrystalline and nanocrystalline TFT modeling ................. 28 Chapter 3. Device Design, Fabrication and Characterization ........ 32 3.1Device Design .................................... 32 3.1-1 Layout Design ................................ 34 3.1-2 ZnO TFTs................................... 35 3.1-3 GZO TFTs .................................. 36 3.1-4 GZO Delta-doped ZnO TFTs .................. 37 3.2 Device Fabrication................................. 39 3.3 Device Characterization............................. 40 3.3-1 thin film crystallinity ............... 40 3.3-2 ZnO TFTs................................... 41 3.3-3 GZO TFTs .................................. 44 3.3-4 GZO Delta-doped ZnO TFTs ..................... 50 Chapter 4. Device Modeling......................... 55 4.1 The analytical Models............................. 56 4.1-1 Grain Boundary .............................. 56 4.1-2 Field Effect Mobility............................ 66 4.1-3 Current-Voltage Relationship.................. 68 4.2 Physical Analysis................................... 73 4.2-1 The Effect of trap density in the Grain Boundaries .............. 75 4.2-2 The Effect of grain size ......................... 80 Chapter 5. Conclusion and Future works ................. 86 5.1 Conclusions ................................... 86 5.2 Recommendations of Future works ............ 88 Appendix: References .......................... 89 | |
| dc.language.iso | en | |
| dc.title | 奈米晶氧化鋅薄膜電晶體之元件物理模型與特性分析 | zh_TW |
| dc.title | Physical Modeling and Device Characterization of Nanocrystalline ZnO-based Thin Film Transistors | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 胡振國,彭隆瀚,陳建彰,吳育任 | |
| dc.subject.keyword | 氧化鋅,薄膜電晶體,奈米晶,物理模型,軟性電子, | zh_TW |
| dc.subject.keyword | ZnO,thin film transistor,nanocrystalline,physical model,flexible electronics, | en |
| dc.relation.page | 90 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-06 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
| 顯示於系所單位： | 光電工程學研究所 | |
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