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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45488完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 江簡富(Jean-Fu Kiang) | |
| dc.contributor.author | Bo-Chan Chen | en |
| dc.contributor.author | 陳柏誠 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:22:59Z | - |
| dc.date.available | 2011-10-05 | |
| dc.date.copyright | 2009-10-05 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-10-01 | |
| dc.identifier.citation | [1] K. W. Yu et al., “A 26 GHz low-noise amplifier in 0.18 μm CMOS technology, ”IEEE Int. Symp. Electron, pp. 93-98, Dec. 2003.
[2] H. -L. Tu, T. -Y. Yang, K. -H. Liang, and H. -K. Chiou, “A 30-GHz 10-dB low noise amplifier using standard 0.18 μm CMOS technology,” Microwave Opt. Technol. Lett., vol. 49, no. 3, pp. 647-649, Mar. 2007. [3] K. W. Yu, Y. L. Lu, D. C. Chang, V. Liang, and M. F. Chang, “K-band low-noise amplifiers using 0.18 μm CMOS technology,” IEEE Microwave Wireless Comp. Lett., vol. 14, no. 3, pp. 106-108, Mar. 2004. [4] W. -M. Cha, Z. -H. Hsu, and C. F. Jou, “Ka-band 0.18 μm CMOS low noise amplifier with 5.2 dB noise figure,” Microwave Opt. Technol. Lett., vol. 49, no. 5, pp. 1187-1189, May 2007. [5] K. Yamanaka, K. Yamauchi, K. Mori, Y. Ikeda, H. Ikematsu, N. Tanahashi, and T. Takagi, “Ku-band low noise MMIC amplifier with bias circuit for compensation of temperature dependence and process variation,” IEEE MTT-S Int. Microwave Symp., vol. 3, pp. 1427-1430, 2002. [6] S. C. Shin et al., “A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology,” IEEE Microwave Wireless Comp. Lett., vol. 15, no. 7, pp. 448-450, July 2005. [7] T. Das, A. Gopalan, C. Washburn and P.R. Mukund, “Self-Calibration of Input-Match in R.F. Front-end Circuitry,” IEEE Trans. Circuits Syst. II, vol. 52, no. 12, pp. 821-825, Dec. 2005. [8] Y. Cui, B. Chi, M. Liu, Y. Zhang, Y. Li, and Z. Wang, “Process variation compensation of a 2.4 GHz LNA in 0.18 μm CMOS using digitally switchable capacitance,” IEEE Int. Symp. Circuits Syst., pp. 2562-2565, May 2007. [9] M. S. Heutmaker, “Architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan”, IEEE Commun. Mag., pp. 98-102, June 1999. [10] Y. Miminom, M. Hirata, K. Nakamura, K. Sakamoto, Y. Aoki and S. Kuroda, “High gain-density K-band p-HEMT LNA MMIC for LMDS and satellite communication,” IEEE MTT-S Int. Microwave Symp., pp. 17-20, 2000. [11] S. Pruvost, I. Telliez, F. Danneville, A. Chantre, P. Chevalier, G. Dambrine, and S. Lepilliet, “A compact low noise amplifier in SiGe:C BiCMOS technology for 40 GHz wireless communications,” IEEE Radio Freq. Integ. Circuits Symp., pp. 565-568, 2005. [12] P. J. Riemer et al., “Ka-band (35 GHz) 3-stage SiGe HBT low noise amplifier,” IEEE MTT-S Int. Microw. Symp., pp. 1037-1040, June 2005. [13] F. Ellinger, R. Vogt, and W. Bchtold, “Calibratable adaptive antenna combiner at 5.2 GHz with high yield for PCMCIA card integration,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 2714V2720, Dec. 2000. [14] K. Yamauchi, Y. Iyama, M. Yamaguchi, Y. Ikeda, and T. Takagi, “X-band MMIC power amplifier with an on-chip temperature-compensation circuit,” IEEE MTT-S Int. Microwave Symp., vol. 2, pp. 1071-1074, May 2001. [15] Y. Su and K. O. Kenneth, “An 800-gW 26-GHz CMOS tuned amplifier,” RFIC, pp. 151-154, 2006. [16] S. -H. Yen and Y. VS. Lin, “Ka-band low noise amplifier using standard 0.18gm CMOS technology,” Electron. Lett., vol. 42, no. 16, pp. 1187-1189, Aug. 2006. [17] X. Guan and A. Hajimiri, “24-GHz CMOS front end,”IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 368V373, Feb. 2004. [18] J. Wadatsumi, S. Kousai, D. Miyashita, and M. Hamada, “A 1.2 V, 0.1-6.0 GHz, twostage differential LNA using gain compensation scheme,” IEEE Silicon Monolithic Integ. Circuits RF Symp., pp. 175-178, Jan. 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45488 | - |
| dc.description.abstract | 一24 GHz低雜訊放大器以CMOS 0.18 um製程來設計並實現，此低雜訊放大器在24 GHz具有15.9 dB的增益及3.3 dB的雜訊指數，P1dB與IIP3分別為-0.91 dBm及-11.7 dBm。此低雜訊放大器在1.8伏特的電源供應下，共消耗21.4 mA的電流及38.5 mW的功率。
一具有閘極偏壓電路的24 GHz低雜訊放大器以CMOS 0.18 um製程來設計並實現，此低雜訊放大器在24 GHz具有12.7 dB的增益及3.77 dB的雜訊指數，採用電流重複利用的架構來降低功耗，在1.8伏特的電源供應下消耗28.9 mW的功率；所提出的閘極偏壓電路，可以使增益因為溫度差異所造成的變動範圍從4.53 dB減少為2.85 dB，使增益因為製程變異所造成的變動範圍從5 dB減少為3.96 dB。 | zh_TW |
| dc.description.abstract | A 24 GHz three-stage low-noise amplifier is designed and implemented in a 0.18 μm CMOS technology. The LNA has a gain of 15.9 dB and minimum noise figure of 3.3 dB at 24 GHz. The input 1-dB compression point (P1dB) and third order intercept point (IIP3) are −11.7 dBm and −0.91 dBm, respectively. This LNA consumes a total current of 21.4 mA and power of 38.5 mW on a 1.8 V power supply.
A 24 GHz low-noise amplifier with gate-bias circuit is designed and implemented using a 0.18 μm CMOS technology. The LNA has a gain of 12.7 dB and minimum noise figure of 3.77 dB at 24 GHz. It adopts a current-reuse technique to reduce the power consumption to 28.9 mW at 1.8 V power supply. The proposed bias circuit reduces the gain variation range due to temperature change from 4.53 dB to 2.85 dB, and that due to process change from 5 dB to 3.96 dB. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:22:59Z (GMT). No. of bitstreams: 1 ntu-98-R95942007-1.pdf: 2529834 bytes, checksum: 278cf612a093766dc202ca63e02454c3 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Abstract i
Table of Contents iii List of Figures v List of Tables vi Acknowledgment viii 1 Introduction 1 2 A 24 GHz CMOS Low-Noise Amplifier 2 2.1 Introduction . . . . . . . . . . . . . . . . . . . 2 2.2 Circuit Implementation . . . . . . . . . . . . . . 3 2.3 Results and Discussions . . . . . . . . . . . . . .5 3 A 24 GHz CMOS Low-Noise Amplifier with Compensation Circuit for Temperature and Process Variations 10 3.1 Introduction . . . . . . . . . . . . . . . . . . .10 3.2 Circuit Implementation of LNA . . . . . . . . . . 12 3.3 Compensation Circuit . . . . . . . . . . . . . . .13 3.4 Simulations and Discussions . . . . . . . . . . . 15 3.5 Measured Results and Discussions . . . . . . . . .16 4 Conclusions 21 Bibliography 22 Biographical Note 24 | |
| dc.language.iso | en | |
| dc.subject | 製程變異 | zh_TW |
| dc.subject | 24GHz | zh_TW |
| dc.subject | LNA | zh_TW |
| dc.subject | 閘極偏壓電路 | zh_TW |
| dc.subject | 溫度 | zh_TW |
| dc.subject | 24 GHz | en |
| dc.subject | temperature | en |
| dc.subject | process change | en |
| dc.subject | LNA | en |
| dc.subject | gate-bias circuit | en |
| dc.title | 24 GHz低雜訊放大器之研製 | zh_TW |
| dc.title | Design of 24 GHz Low-Noise Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 莊晴光(Ching-Kuang C. Tzuang),呂良鴻(Liang-Hung Lu) | |
| dc.subject.keyword | 24GHz,LNA,閘極偏壓電路,溫度,製程變異, | zh_TW |
| dc.subject.keyword | 24 GHz,LNA,gate-bias circuit,temperature,process change, | en |
| dc.relation.page | 24 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-10-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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| ntu-98-1.pdf 未授權公開取用 | 2.47 MB | Adobe PDF |
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