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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Tzu-Kuan Wu | en |
dc.contributor.author | 吳子寬 | zh_TW |
dc.date.accessioned | 2021-05-14T17:42:53Z | - |
dc.date.available | 2020-08-20 | |
dc.date.available | 2021-05-14T17:42:53Z | - |
dc.date.copyright | 2015-08-20 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-13 | |
dc.identifier.citation | [1] Moore, Electronics, Vol 38, No. 8, 1965
[2] Bohr, M., “The evolution of scaling from the homogeneous era to the heterogeneous era”, in IEEE International Electron Devices Meeting (IEDM), 2011, pp. 1.1.1 - 1.1.6. [3] Salahuddin, Sayeef, “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?” in IEEE International Electron Devices Meeting (IEDM), 2008, pp. 1-4. [4] Chenming Hu, lecture at NDL, 2011 [5] S. Oktyabrsky and P.D. Ye, Fundamentals of III-V Semiconductor MOSFET, Springer, 2009. [6] J.A. del Alamo et al, “InGaAs MOSFETs for CMOS: Recent Advances in Process Technology” in IEEE International Electron Devices Meeting (IEDM), 2013, pp. 2.1.1 - 2.1.4. [7] D.-H. Kim et al, “High-Performance III-V devices for future logic applications” in IEEE International Electron Devices Meeting (IEDM), 2014, pp. 25.2.1 - 25.2.4. [8] J.A. del Alamo et al, “Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies”, Massachusetts Institute of Technology(MIT), 2014 [9] D.K. Schroder, Semiconductor material and device characterization, Wiley, 2006. [10] GILLES DAMBRINE et al, “A New Method for Determining the FET Small-Signal Equivalent Circuit,” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 36, NO. 7, JULY 1988 [11] David Lovelace et al, “EXTRACTING SMALL-SIGNAL MODEL PARAMETERS OF SILICON MOSFET TRANSISTORS” in MTTT-S Digest, pp.865,1994 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/4515 | - |
dc.description.abstract | 自1965年Moore提出摩爾定律(Moore’s Law),30、40年來確實依其預測由單一晶片中數千個電晶體呈幾何式上升至數十億個電晶體,而尺寸的微縮同時也帶來操作頻率由數百萬赫茲提升至數百兆赫茲的好處,但是在電晶體尺寸減少的過程中,每一世代皆需要解決”短通道效應”(short channel effects)(SCEs),解決方法除了改進閘極氧化層外,亦可透過3D結構,如鰭式場效電晶體(FinFET)。
本論文第一部分,首先探討主流的矽電晶體,發現鰭式場效電晶體相較於平面式電晶體除了截止狀態的短通道效應控制較佳外,亦有在相同面積(footprint)下導通狀態電流較大的優勢。當鰭寬度(WFin)由200奈米微縮至30奈米時,截止電流從甚至無法達到臨界電流的要求改善至汲極引致能障下降為78 mV/V。當鰭高度(HFin)由30奈米增加至110奈米時,其導通狀態電流由179 μA/μm增加至422 μA/μm。 本論文第二部分,接著探討被視為下世代n型電晶體的砷化銦鎵金氧半高載子遷移率電晶體,發現平面式電晶體中,當阻擋層厚度由302埃減少至158埃時,開關比由1個數量級增加至6個數量級,但導通狀態電流由373 μA/μm降低至95 μA/μm;鰭式電晶體中,當鰭寬度由6微米微縮至2微米時,臨界電壓由-4伏特上升至-2伏特,導通狀態電流由192 μA/μm降低至1.29 μA/μm。未來需最佳化鰭寬度與阻擋層厚度,以同時得到最佳的導通狀態與截止狀態。 本論文第三部分,探討砷化銦鎵高載子遷移率電晶體之高頻電特性,透過建立其小訊號模型,發現當閘極長度(LG)由10微米微縮至2微米時,其截止頻率由1.32 GHz增加至11.54 GHz;當閘極到源汲極距離(LGS/LGD)由20微米微縮至5微米時,其截止頻率由10.77 GHz增加至11.54 GHz;未來將微縮閘極長度、閘極到源/汲極距離至數百甚至數十奈米,並透過不同等效閘極寬度(閘極寬度與閘極指數目的乘積)近一步探討閘極寬度與多指型結構對截止頻率的影響,以期能設計出最佳化的元件佈局進一步提高元件的截止頻率。 | zh_TW |
dc.description.abstract | Since Moore’s law was proposed in 1965, transistor numbers have been increased from thousands to billions on a single chip. While the size of the transistor is scaling, the operating frequency is also enhanced from MHz toward THz. To maintain the scaling path and benefit from both price and performance boosting, short channel effects (SCEs) must be solved in each generation. To suppress SCEs, except for improving gate oxides, it can be achieved by 3D structures, i.e. fin field-effect transistors (FinFETs).
In this thesis, we focus on suppressing SCEs in the Si FinFET and the InGaAs Metal-Oxide-Semiconductor high-electron-mobility transistor (MOSHEMT). Also we investigate the radio frequency electronic characteristics of HEMT. Firstly, we show the influence of fin structure on mainstream Si FinFET. Compared with planar MOSFET, FinFET is superior not only in the SCEs control but also in the on-state current under same footprint. The off-state performance is improved from off-state leakeage current larger than threshold current definition to DIBL = 78 mV/V, as the fin width (WFin) shrinking from 200 to 30 nm. The on-state current increases from 179 to 422 μA/μm, as the fin height (HFin) increasing from 30 to 110 nm. Secondly, we investigate the gate recess and the fin structure effect in the InGaAs MOSHEMT which is regarded as next generation n-channel transistor. In planar devices, as the barrier thickness decreases from 302 to 158 Å, the on/off ratio increases from 1 to 6 orders, but the on-state current decreases from 373 to 95 μA/μm. In 3D devices, as the fin width decreases from 6 to 2 μm, threshold voltage increases from -4 to -2 V, but the on-state current decreases from 192 to 1.29 μA/μm. The barrier thickness and the fin width need further optimization to achieve superior both on-state and off-state performance. Thirdly, we investigate the radio frequency electronic characteristic of HEMT by building the small signal model. The cut-off frequency (fT) increases from 1.32 to 11.54 GHz, as gate length (LG) decreases from 10 to 2 μm. The fT increases from 10.77 to 11.54 GHz, as the gate to source/drain distance (LGS/LGD) decreases from 20 to 5 μm. In the future, we are planing on shrinking LG, LGS/LGD and further investigating of the influence of the gate width and the multi-gate structure via different effective gate width, the gate width times the gate number, in order to obtain the optimized layout to enhance the cut-off frequency. | en |
dc.description.provenance | Made available in DSpace on 2021-05-14T17:42:53Z (GMT). No. of bitstreams: 1 ntu-104-R02943110-1.pdf: 12628133 bytes, checksum: 630535f713bd34d9217e25875191a9bd (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 誌謝 I
中文摘要 II ABSTRACT V 目錄 VII 圖目錄 IX 表目錄 XV 第1章 緒論 1 1.1 背景介紹 1 1.2 短通道效應 6 1.3 論文概述 9 第2章 矽鰭式場效電晶體之製作與電特性分析 10 2.1 矽鰭式場效電晶體簡介 10 2.2 矽鰭式場效電晶體之製作流程 14 2.3 矽鰭式場效電晶體之電性分析 16 2.4 本章結論 23 第3章 砷化銦鎵高載子遷移率電晶體之製作與電特性分析 24 3.1 背景介紹 24 3.1.1 三五族電晶體簡介 24 3.1.2 高載子遷移率電晶體簡介 26 3.1.3 砷化銦鎵高載子遷移率電晶體發展簡介 26 3.2 砷化銦鎵金氧半高載子遷移率電晶體之製作流程 30 3.3 砷化銦鎵金氧半高載子遷移率電晶體之電性分析 34 3.3.1 電流電壓特性分析 34 3.3.2 載子遷移率萃取方式 40 3.4 本章結論與未來研究方向 46 第4章 砷化銦鎵高載子遷移率電晶體之高頻電特性分析與小訊號模型 48 4.1 背景介紹 48 4.1.1 高頻元件應用簡介 48 4.1.2 小訊號簡介 50 4.1.3 雙埠網路(Two-port network)簡介 50 4.1.4 使用雙埠網路參數之數學技巧 52 4.2 適於高頻量測之砷化銦鎵高載子遷移率電晶體之製作流程 55 4.3 去嵌化(De-embedding)之目的與流程 57 4.4 砷化銦鎵高載子遷移率電晶體之高頻電特性分析 63 4.4.1 高載子遷移率電晶體之小訊號模型簡介 63 4.4.2 零偏壓萃取法簡介 65 4.4.3 砷化銦鎵高載子遷移率電晶體之小訊號模型建立實例 70 4.4.4 元件佈局(Layout)與尺寸對小訊號參數之影響 78 4.5 本章結論與未來研究方向 90 第5章 論文總結與未來展望 91 參考文獻 93 | |
dc.language.iso | zh-TW | |
dc.title | 閘極蝕刻與鰭式結構對於場效電晶體特性影響與高載子遷移率電晶體高頻電特性之研究 | zh_TW |
dc.title | Investigation of the Influence of Gate Recess and Fin Structure
in the Field-Effect Transistors and the High Frequency Response in the High-electron-mobility Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊英杰(Ying-Jay Yang),林浩雄(Hao-Hsiung Lin),陳敏璋(Miin-Jang Chen),張書維(Shu-Wei Chang) | |
dc.subject.keyword | 鰭式場效電晶體,砷化銦鎵金氧半高載子遷移率電晶體,射頻電特性,截止頻率,閘極蝕刻,短通道效應, | zh_TW |
dc.subject.keyword | Fin Field-Effect Transistor (FinFET),InGaAs Metal-Oxide-Semiconductor high-electron-mobility transistor (MOSHEMT),radio frequency,cut-off frequency,gate recess,short channel effects (SCEs), | en |
dc.relation.page | 93 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2015-08-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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