請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45030完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Wei-Shan Ye | en |
| dc.contributor.author | 葉偉賢 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:01:55Z | - |
| dc.date.available | 2013-03-11 | |
| dc.date.copyright | 2010-03-11 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-02-22 | |
| dc.identifier.citation | [1] Robert W. Erickson ; Dragan Maksimovic`, “Fundamentals of Power Electronics , Second Edition” 2001 by Kluwer Academic Publishers
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45030 | - |
| dc.description.abstract | 本論文闡述一個雙模式控制與線性調整閘級驅動技術的直流電壓轉換器，並以台積電0.35-μm 2P4M 3.3V/5V Mixed Signal CMOS製程製作。當發生暫態變化時，使用遲滯控制的方式來飽和閘極驅動訊號的責任週期，藉此來加快暫態反應時間；而穩態時，使用脈衝寬度調變控制來維持相同的切換頻率。針對輕載時的效率，採用預先決定最佳化輸出功率電晶體的閘級驅動電壓，藉由改變電壓來減少閘級驅動損失。
依據量測的結果，本晶片的切換頻率設定在1MHz，暫態回復時間可降為25μs，提出的閘級驅動技術可以在負載為3mA時效率提升了4%，最高效率為93.2%，輸入電壓穩定度與負載穩定度分別為0.85 %/V與0.83 %/mA，輸出電壓的漣波值為21mV。晶片總面積占3.07 mm2，而其它的量測結果也包含在本論文內。 | zh_TW |
| dc.description.abstract | This thesis presents a dual-mode control and linear-scaling gate drive voltage technique of DC-DC buck converter in a standard 0.35-μm 2P4M 3.3V/5V Mixed Signal CMOS process. The dual-mode control enables hysteretic control during transient for fast transient recovery time by saturating the duty cycle of gate-drive signal, and the PWM control is enabled at steady state to preserve the advantage of fixed switching frequency. For light-load efficiency, the predetermined optimal gate drive voltage of the power MOSFETs is used by changing its value to reduce gate-driving loss.
According to the measurement results, the switching frequency of the chip operates at 1MHz, and the transient recovery time of the DC-DC buck converter can be improved to 25μs. The proposed gate drive technique can attain about 4% incremental enhancement when the load current is 3mA, and the maximum efficiency is 93.2%. The line regulation and load regulation are 0.85 %/V and 0.83 %/mA, respectively, and the output ripple voltage is less than 21mV. The chip size occupies 3.07mm2, and the other detailed measurement is included in this thesis, too. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:01:55Z (GMT). No. of bitstreams: 1 ntu-99-R96943162-1.pdf: 14464728 bytes, checksum: 79f815b1f76a2427cf6d7d56f84425ea (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III Table of Contents IV List of Figures VI List of Tables X Chapter 1 Introduction 1 1.1 Motivation 3 1.2 Thesis Organization 6 Chapter 2 Fundamental and Survey of DC-DC Buck Converter 7 2.1 Fundamental of DC-DC Buck Converter 7 2.1.1 Efficiency 7 2.1.2 Regulation 8 2.1.3 Transient Response 10 2.1.4 DC-DC Buck Converter Operation 13 2.1.5 Estimation of Output Voltage Ripple 18 2.1.6 Feedback-Loop Stabilization 20 2.2 Paper survey 24 Chapter 3 Proposed Architecture 34 3.1 Specification of DC-DC Buck Converter 34 3.2 System Architecture 34 3.3 Dual Mode Control 36 3.4 Linear-Scaling Gate Drive Voltage Technique 38 Chapter 4 Circuit Implementation and Simulation Results 45 4.1 Error Amplifier Circuit 45 4.2 Comparator Circuit 47 4.3 Ramp Generator Circuit 51 4.4 Hysteretic Comparator Circuit 49 4.5 Current Sensor Circuit 53 4.6 Peak Detector Circuit 55 4.7 Linear-Scaling Gate Drive Voltage (VDDN and VDDP) Generator Circuit 56 4.8 Gate Driver with Dead Time Control 58 4.9 Simulation Results 60 Chapter 5 Experiment Results 71 5.1 Measurement Setup 71 5.2 Measurement Results 79 5.3 Comparison & Discussion 87 Chapter 6 Conclusion and Future Work 89 6.1 Conclusion 89 6.2 Future Work 89 Bibliography 91 | |
| dc.language.iso | en | |
| dc.subject | 遲滯控制 | zh_TW |
| dc.subject | 直流電壓轉換器 | zh_TW |
| dc.subject | 脈衝寬度調變控制 | zh_TW |
| dc.subject | 閘級驅動電壓 | zh_TW |
| dc.subject | gate drive voltage | en |
| dc.subject | pulse-width-modulation control | en |
| dc.subject | hysteretic control | en |
| dc.subject | DC-DC converter | en |
| dc.title | 一個採用雙模式控制與線性調整閘級驅動技術之直流降壓式轉換器 | zh_TW |
| dc.title | A Dual-Mode Control and Linear-Scaling Gate Drive Voltage Technique of DC-DC Buck Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳怡然,陳昭宏,陳建中 | |
| dc.subject.keyword | 直流電壓轉換器,脈衝寬度調變控制,遲滯控制,閘級驅動電壓, | zh_TW |
| dc.subject.keyword | DC-DC converter,pulse-width-modulation control,hysteretic control,gate drive voltage, | en |
| dc.relation.page | 97 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-02-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-99-1.pdf 未授權公開取用 | 14.13 MB | Adobe PDF |
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