改進且提高信賴值之LDPC解碼節點處理器

Abstract

LDPC(Low-Density Parity-Check)由於其優異的錯誤更正能力可以逼近理論值，所以在近期受到高度的關注。知名的sum-product 有著很好的解碼獲益，但是在實作方面上有較高的複雜度。為了解決這個問題，一些近似演算法像是scaling min-sum被提出。雖然複雜度比起sum-product變低, 但是其解碼效能也遭受到一些損失。因此，在這篇論文中我們試著提出一個修改過的scaling min-sum演算法。這個演算法藉由在解碼過程中有條件地提高傳播的信賴值來改善解碼效能。同時，我們也提出並且實作修改後演算法的串列式硬體架構。模擬結果顯示當位元錯誤率為10-7時我們可以獲得大約0.75dB的獲益在802.16e，0.8dB的獲益在802.11n。而FPGA實作結果顯示我們只增加了3.6%的硬體成本。

Low-Density Parity-Check (LDPC) codes have received great attention in last decade owing to their capacity-approaching performance. The well-known sum-product algorithm (SPA) achieves very good coding gain but it is too complex for hardware implementation. To solve this problem, several approximated algorithms such as scaling min-sum (SMS) are proposed. However, SMS suffers from the performance degradation compared to SPA. Thereby, in this thesis we try to propose a modified scaling min-sum algorithm. Our algorithm improves the coding performance by enhancing the belief propagated conditionally during decoding process. We also propose and implement the serial hardware architecture of our proposed algorithm. Simulation result shows we can obtain about 0.75dB coding gain while BER=10-7 in 80216e and about 0.8dB coding gain in 802.11n. The FPGA implementation result shows that our architecture only adds 3.6% hardware cost.