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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44670完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Kam-Tou Sio | en |
| dc.contributor.author | 蕭錦濤 | zh_TW |
| dc.date.accessioned | 2021-06-15T03:52:37Z | - |
| dc.date.available | 2011-07-28 | |
| dc.date.copyright | 2010-07-28 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-07 | |
| dc.identifier.citation | [1] J.-Y. Hsieh and S.-J. Ruan, “Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm,” Asia and South Pacific Design Automation Conference, Seoul, Korea, 2008.
[2] I. Y. L. Hsiao et al., “Power modeling and low-power design of content addressable memories,” in Proc. IEEE Int Symp. Circuits and Systems (ISCAS), vol. 4, pp. 926-929, May 2001. [3] X. Liang, et al., “Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques,” Computer-aided design, San Jose, California, 2007. [4] C.-S. Lin, et al., “Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory,” Circuits and Systems, vol.2, pp. 319-324, 2002. [5] C.-S. Lin, et al., “A low-power precomputation-based fully parallel content-addressable memory,” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, pp. 654-662, Apr. 2003. [6] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 712-727, 2006. [7] S.-J Ruan et al., “Low Power Design of Precomputation-Based Content-Addressable Memory,” Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 331-335, 2008. [8] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin,T. Mudge, and R. B. Brown, “Mibench: A free, commercially representative embedded benchmark suite,” in Proc. IEEE Int. Workshop on Workload Characterization(WWC) , pp. 3–14, Dec. 2001. [9] N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi, “Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0,” Proc. 40th Ann. IEEE/ACM Int’l Symp. Microarchitecture (MICRO 07), IEEE, pp. 3-14, 2007. [10] T. Jamil, “RAM versus CAM,” IEEE Potentials, pp. 26-29, April/May 1997. [11] S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, 'A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router,' IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853-861, Apr. 2005. [12] I. Arsovski and A. Sheikholeslami, “A current-saving match-line sensing scheme for content-addressable memories,” in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 304-494 vol.1, 2003. [13] V. Chaudhary, T. H. Chen, F. Sheerin, and L. T. Clark, “Critical race-free low-power nand match line content addressable memory tagged cache memory,” IET Computers & Digital Techniques, vol. 2, no. 1, pp. 40-44, Jan. 2008. [14] K. J. Schultz, “Content-addressable memory core cells: a survey,” Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997. [15] D. Brooks, et al., 'Wattch: a framework for architectural-level power analysis and optimizations,' SIGARCH Comput. Archit. News, vol. 28, pp. 83-94, 2000. [16] N. Vijaykrishnan, et al., 'Energy-driven integrated hardware-software optimizations using SimplePower,' presented at the Proceedings of the 27th annual international symposium on Computer architecture, Vancouver, British Columbia, Canada, 2000. [17] M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir. “IDAP: A tool for high level power estimation of custom array structures”, in International Conference on Computer Aided Design (ICCAD), Nov 2003. [18] M. Mamidipaka, K. Khouri, and N. Dutt. “A methodology for accurate modeling of energy dissipation in array structures”, in VLSI Design, pages 320–325, 2003. [19] Neil Weste, David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44670 | - |
| dc.description.abstract | 內容可定址記憶體是一種利用隨機靜態存取記憶體作爲記憶單元的裝置。它在查找IP位址的網路路由器、封包傳送以及封包分類上有著相當大的利用價值。爲了迎合市場上不同的需要，進而發展出各種不同的內容可定址記憶體，例如預先計算型內容可定址記憶體。本篇論文發展一套可以在早期估算的能量表示方法，給予電路設計師在早期設計時估計晶片之功率消耗以及功率分佈。對於所建立的方法，大幅縮短時間而又能夠產出令人滿意的準確率，是本篇論文的主要目的。在此篇論文裡，提出一種稱爲CAM拼圖的方法。其基本原理是先用HSPICE模擬建立出各種用功能可區分的小模型，再把它們組合起來，形成一個完整的CAM系統。這個方法不單可以分析普通的內容可定址記憶體，亦可應用在預先計算型的內容可定址記憶體上。另外，此方法亦同樣用作估計週邊電路的功率消耗，例如位址解碼器電路以及資料I/O驅動電路等等較爲耗電的裝置。實驗結果表示，應用此方法作爲內容可定址記憶體的分析，可以在極短的模擬時間內得到82%的模型準確率，以及94%的系統準確率。而與此方法相比的是在180奈米製程下所進行的HSPICE模擬結果。 | zh_TW |
| dc.description.abstract | Content Addressable Memory (CAM) is a data storage device, utilizing the Static Random Access Memory (SRAM) cell. CAMs are very popular especially implemented in network routers for IP address lookup, packet forwarding and packet classifications. Up to now, there are many types of CAM to conform to these different implementations. For the purpose to estimate the efficiency and power distribution of all types of CAM, doing preliminary simulation is needed before doing concrete circuit layout. Therefore, a speedy and accurate power analysis method is necessary. Besides, the simulation time of nowadays circuit simulation tool like HSPICE is considerable, especially for high frequency data storage circuits like CAMs. This work established a brand new power model of CAM which is called CAM Puzzle (CAMP), combining the petty models which are extracted from SPICE simulation, simplified into easily analytical power expressions in order to analyse the conventional CAM and pre-computation based content addressable memory (PB-CAM). In addition, this work also estimates the power consumption of CAM peripheral circuits such as address decoder circuit and data I/O. Using CAMP, the power consumption of complete CAM architecture can be estimated with 82% CAM Puzzle model accuracy and 94% entire CAM accuracy compared with SPICE simulation in 0.18μm process. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T03:52:37Z (GMT). No. of bitstreams: 1 ntu-99-R97945018-1.pdf: 3423359 bytes, checksum: 106913d5c4d9e0ff3309fa2879d5ab85 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 摘要 iii Abstract iv Contents v List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Content Addressable Memory (CAM) 2 1.1.1 CAM Cell Array 3 1.1.2 Write Operation of CAM Cell 4 1.1.3 Search Operation of CAM Cell 5 1.2 Pre-computation Based Content Addressable Memory (PB-CAM) 6 1.2.1 Ones Count PB-CAM 9 1.2.2 Block-XOR PB-CAM 10 1.2.3 Gate-Block Selection PB-CAM 10 1.3 RC Model of Wire 12 1.4 HSPICE 14 1.4.1 Introduction of SPICE 14 Chapter 2 Background and Related Work 16 2.1 CACTI: An Integrated Cache Model 16 2.2 Implementation Dependent Array Power (IDAP) 17 2.3 Power Estimation of Match-line Power 18 2.4 Analytical Models of CAM 19 2.5 Empirical Models of CAM 20 2.6 Hybrid Models of CAM 22 Chapter 3 Proposed Approach 23 3.1 Concept of CAM Puzzle 23 3.2 Circuit Segment Method 25 3.2.1 Conventional CAM 25 3.2.2 PB-CAM 26 3.3 Probability Factor 26 3.4 CAM Puzzle’s Power Model 28 3.4.1 Address Decoder 28 3.4.2 Match-line Circuit 29 3.4.3 Data Cell Array 31 3.4.4 Parameter Extractor and Parameter Storage Cell 33 3.4.5 Peripheral Circuits 36 3.5 Cycle Definition 38 3.5.1 Write and Search Cycle Analysis 38 3.5.2 Search Cycle Analysis 39 Chapter 4 Experimental Results 40 4.1 Experimental Environment 40 4.2 Model Database of CAM Puzzle 41 4.3 Simulation Results 41 4.3.1 Power Consumption 41 4.3.2 Power Distribution 42 4.3.3 Model Accuracy of CAM Puzzle 42 4.3.4 System Accuracy of CAM Puzzle 43 Chapter 5 Conclusion 49 References 50 | |
| dc.language.iso | en | |
| dc.subject | 隨機靜態存取記憶體 | zh_TW |
| dc.subject | HSPICE | zh_TW |
| dc.subject | 解碼器 | zh_TW |
| dc.subject | 網路路由器 | zh_TW |
| dc.subject | 內容可定址記憶體 | zh_TW |
| dc.subject | 0.18μm process | en |
| dc.subject | PB-CAM | en |
| dc.subject | SPICE | en |
| dc.subject | CAM | en |
| dc.subject | accuracy | en |
| dc.title | 內容可定址記憶體之功率模型及功能為基礎之電路分割方法 | zh_TW |
| dc.title | CAM Puzzle: Power Model and Function-Based Circuit Segment Method of Content Addressable Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 許孟超,蔡坤霖,林振群,阮聖彰 | |
| dc.subject.keyword | 內容可定址記憶體,隨機靜態存取記憶體,網路路由器,解碼器,HSPICE, | zh_TW |
| dc.subject.keyword | CAM,SPICE,PB-CAM,accuracy,0.18μm process, | en |
| dc.relation.page | 52 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-07-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 生醫電子與資訊學研究所 | zh_TW |
| 顯示於系所單位： | 生醫電子與資訊學研究所 | |
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| ntu-99-1.pdf 未授權公開取用 | 3.34 MB | Adobe PDF |
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